Engineering:ETRAX CRIS
The ETRAX CRIS is a RISC ISA and series of CPUs designed and manufactured by Axis Communications for use in embedded systems since 1993.[1] The name is an acronym of the chip's features: Ethernet, Token Ring, AXis - Code Reduced Instruction Set. Token Ring support has been taken out from the latest chips as it has become obsolete.
Types of chips
The CGA-1 (Coax Gate Array) was the first microprocessor developed by Axis Communications. It contains IBM 3270 (coax) and IBM 5250 (Twinax) communications. The chip has a microcontroller and various I/O's such as serial and parallel. The CGA-1 chip was designed by Martin Gren and Staffan Göransson.[2]
ETRAX
- In 1993, Axis developed the ETRAX-1 Ethernet Controller, which has 10 Mbit/s Ethernet and Token Ring controllers.
- In 1995, Axis introduced the ETRAX-4 SoC which contains a Ethernet Controller, CPU, Memory Interface, SCSI controller, and parallel and serial I/O. [3]
- In 1997, Axis introduced the ETRAX 100 SoC which features a 10/100 Mbit/s Ethernet Controller, ATA controller, and Wide SCSI controller. The chip introduced on-chip unified instruction and data cache along with direct memory access.[4]
ETRAX 100LX
In 2000, Axis Introduced the ETRAX 100LX SoC which features a MMU, USB controller, and SDRAM interface. The CPU is capable of 100 MIPS. The chip is able to run the Linux kernel without modifications except for low-level support.[5] The chip's maximum TDP is 0.35 Watts. As of Linux kernel 4.17, the architecture has been dropped due to being obsolete.[6]
Specifications:
- 32-bit RISC CPU core
- 10/100 Mbit/s Ethernet controller
- 4 asynchronous serial ports
- 2 synchronous serial ports
- 2 USB ports
- 2 Parallel ports
- 4 ATA (IDE) ports
- 2 Narrow SCSI ports (or 1 Wide)
- Support for SDRAM, Flash, EEPROM, SRAM
ETRAX 100LX MCM
The ETRAX 100LX MCM is based on the ETRAX 100 LX. The chip has internal flash memory, SDRAM, and an Ethernet PHYceiver. The Chip can come with 2 MB flash and 8 MB SDRAM or 4 MB flash and 16 MB SDRAM.
ETRAX FS
Introduced in 2005 with full Linux 2.6 support, the chip features:
- A 200 MIPS 32-bit RISC CRIS CPU core with 16 kB instruction and data cache
- 128 kB on-chip RAM
- Two 10/100 Mbit/s Ethernet controllers
- Crypto accelerator supporting AES, DES, Triple DES, SHA-1, and MD5
- I/O processor supporting PC-Card, PCI, USB, SCSI and ATA
ARTPEC
References
- ↑ axis.com - Axis Chip Development History
- ↑ "30 years of milestones". http://www.axis.com/files/sales/axis_milestones_30years_1401_lo.pdf.
- ↑ Zander, Per. "Axis Communications - A World Of Intelligent Networks". https://www.eit.lth.se/fileadmin/eit/courses/eitn30/Forel/ii_etrax_13.pdf.
- ↑ (in en) ETRAX 100: technical specifications. 1999-01-01. https://librarytechnology.org/document/4107.
- ↑ The linux kernel source-code under /arch/cris contained the low-level CPU-specific additions required to make the Linux kernel able to run on the ETRAX/Cris CPUs. (See for example https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/cris?h=v4.13-rc4)
- ↑ "Linux-Kernel Archive: [PATCH 00/16] remove eight obsolete architectures". http://lkml.iu.edu/hypermail/linux/kernel/1803.1/06845.html.
External links
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