Engineering:Field-programmable analog array

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Short description: Integrated device containing configurable analog blocks and interconnects between these blocks

A field-programmable analog array (FPAA) is an integrated circuit device containing computational analog blocks (CAB)[1][2] and interconnects between these blocks offering field-programmability. Unlike their digital cousin, the FPGA, the devices tend to be more application driven than general purpose as they may be current mode or voltage mode devices. For voltage mode devices, each block usually contains an operational amplifier in combination with programmable configuration of passive components. The blocks can, for example, act as summers or integrators.

FPAAs usually operate in one of two modes: continuous time and discrete time.

  • Discrete-time devices possess a system sample clock. In a switched capacitor design, all blocks sample their input signals with a sample and hold circuit composed of a semiconductor switch and a capacitor. This feeds a programmable op amp section which can be routed to a number of other blocks. This design requires more complex semiconductor construction. An alternative, switched-current design, offers simpler construction and does not require the input capacitor, but can be less accurate, and has lower fan-out - it can drive only one following block. Both discrete-time device types must compensate for switching noise, aliasing at the system sample rate, and sample-rate limited bandwidth, during the design phase.
  • Continuous-time devices work more like an array of transistors or op amps which can operate at their full bandwidth. The components are connected in a particular arrangement through a configurable array of switches. During circuit design, the switch matrix's parasitic inductance, capacitance and noise contributions must be taken into account.

Currently there are very few manufactures of FPAAs. On-chip resources are still very limited when compared to that of an FPGA. This resource deficit is often cited by researchers as a limiting factor in their research.

History

The LYAPUNOV-1 uses a 4x8 grid of FPAA chips.

The term FPAA was first used in 1991 by Lee and Gulak.[3] They put forward the concept of CABs that are connected via a routing network and configured digitally. Subsequently, in 1992[citation needed] and 1995[4] they further elaborated the concept with the inclusion of op-amps, capacitors, and resistors. This original chip was manufactured using 1.2 µm CMOS technology and operates in the 20 kHz range at a power consumption of 80 mW.

Pierzchala et al introduced a similar concept named electronically-programmable analog circuit (EPAC).[5] It featured only a single integrator. However, they proposed a local interconnect architecture in order to try to avoid the bandwidth limitations.

The reconfigurable analog signal processor (RASP) and a second version were introduced in 2002 by Hall et al.[6][7] Their design incorporated high-level elements such as second order bandpass filters and 4 by 4 vector matrix multipliers into the CABs. Because of its architecture, it is limited to around 100 kHz and the chip itself is not able to support independent reconfiguration.

In 2004 Joachim Becker picked up the parallel connection of OTAs (operational transconductance amplifiers) and proposed its use in a hexagonal local interconnection architecture.[8] It did not require a routing network and eliminated switching the signal path that enhances the frequency response.

In 2005 Fabian Henrici worked with Joachim Becker to develop a switchable and invertible OTA which doubled the maximum FPAA bandwidth.[9] This collaboration resulted in the first manufactured FPAA in a 0.13 µm CMOS technology.

In 2016 Dr. Jennifer Hasler from Georgia Tech designed a FPAA system on a chip that uses analog technology to achieve unprecedented power and size reductions.[10]

See also

References

  1. ↑ Hall, Tyson; Twigg, Christopher; Hassler, Paul; Anderson, David (2004). "Application performance of elements in a floating-gate FPAA". 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512). pp. 589–592. doi:10.1109/ISCAS.2004.1329340. ISBN 0-7803-8251-X. 
  2. ↑ Baskaya, F.; Reddy, S.; Sung, Kyu Lim; Anderson, D.V. (August 2006). "Placement for large-scale floating-gate field-programable analog arrays". IEEE Transactions on VLSI Systems 14 (8): 906–910. doi:10.1109/TVLSI.2006.878477. https://www.computer.org/csdl/trans/si/2006/08/01664910-abs.html. 
  3. ↑ E. K. F. Lee; P. G. Gulak (December 1991). "A CMOS Field-programmable analog array". IEEE Journal of Solid-State Circuits 26 (12): 1860–1867. doi:10.1109/4.104162. Bibcode: 1991IJSSC..26.1860L. 
  4. ↑ Lee, E.K.F.; Gulak, P.G. (1995). "A transconductor-based field-programmable analog array". Proceedings ISSCC '95 - International Solid-State Circuits Conference. pp. 198–199. doi:10.1109/ISSCC.1995.535521. ISBN 0-7803-2495-1. 
  5. ↑ Pierzchala, E.; Perkowski, M.A.; Van Halen, P.; Schaumann, R. (1995). "Current-mode amplifier/Integrator for a field-programmable analog array". Proceedings ISSCC '95 - International Solid-State Circuits Conference. pp. 196–197. doi:10.1109/ISSCC.1995.535520. ISBN 0-7803-2495-1. 
  6. ↑ Hall, Tyson S.; Hasler, Paul; Anderson, David V. (2002). "Field-Programmable Analog Arrays: A Floating—Gate Approach". Field Programmable Analog Arrays: A Floating-Gate Approach. Lecture Notes in Computer Science. 2438. pp. 424–433. doi:10.1007/3-540-46117-5_45. ISBN 978-3-540-44108-3. http://uilis.unsyiah.ac.id/opentheses/items/show/3084. 
  7. ↑ Hall, T.S.; Twigg, C.M.; Gray, J.D.; Hasler, P.; Anderson, D.V. (2005). "Large scale field programmable analog arrays for analog signal processing". IEEE Transactions on Circuits and Systems I: Regular Papers 52 (11): 2298–2307. doi:10.1109/TCSI.2005.853401. 
  8. ↑ "A continuous-time field programmable analog array (FPAA) consisting of digitally reconfigurable GM-cells". CiteSeerX 10.1.1.444.8748.[clarification needed]
  9. ↑ "A Continuous-Time Hexagonal Field-Programmable Analog Array in 0.13 µm CMOS with 186MHz GBW". CiteSeerX 10.1.1.444.8748.[clarification needed]
  10. ↑ Suma George; Sihwan Kim; Sahil Shah; Jennifer Hasler; Michelle Collins; Farhan Adil; Richard Wunderlich; Stephen Nease et al. (June 2016). "A Programmable and Configurable Mixed-Mode FPAA SoC". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (6): 2253–2261. doi:10.1109/TVLSI.2015.2504119. 

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