Engineering:GAL22V10
| Design firm | Lattice Semiconductor |
|---|---|
| Type | Series of programmable-logic devices |
The GAL22V10 is a series of programmable-logic devices from Lattice Semiconductor, implemented as CMOS-based generic array logic ICs, and available in dual inline packages or plastic leaded chip carriers. It is an example of a standard production GAL device that is often used in educational settings as a basic programmable-logic device.[1][2][3]
Specifications
The GAL22V10 has 12 input pins, and 10 pins that can be configured as either inputs or outputs, and exists in various switching speeds, from 25 to 4 ns.[1][2][4] Each output is driven by an output-logic macrocell (OLMC), with an output-enable product term, and a variable number of product terms, ranging from eight to sixteen. Each OLMC may be set to output as inverting or non-inverting, and be placed into either registered or combinatorial mode. In registered mode, each macrocell actively uses a D-flip-flop to hold a state under control of the data input from the logic portion of the macrocell and the rising edge of the clock signal, while in combinatorial mode the flip-flop is removed from the macrocell and the outputs are driven directly by the logic. In the latter mode, the pin may also dynamically switch between input and output based on the product term. In either mode the pin value is fed back into the array as a product term. Combinations are set using an E2PROM.[3] The output registers can be preloaded into a potentially invalid state for testing by a GAL22V10 programmer. Inputs and outputs include active pull-ups and are transistor-transistor logic compatible due to high-impedance buffers.[5]
A user electronic signature section is included for details such as user ID codes, revision IDs, or asset tagging on official Lattice Semiconductor units, as well as a static ES section for compatibility with non-Lattice Semiconductor GAL22V10 units. In addition, a security cell is included which, when set, disallows the retrieval of the array logic from the chip, until a new set of logic is set.
Latch-up protection is implemented using n-pullups and a charge pump in the official Lattice Semiconductor models.
Availability
The GAL22V10D had been discontinued by Lattice Semiconductor as of June 2010 with the last shipment in June 2011. No pin-compatible replacements have been offered or recommended by Lattice for this PLD.[6] However, other pin-compatible alternatives exist from other manufacturers (e.g. Atmel ATF22V10).
References
- ↑ 1.0 1.1 Foltz, Heinrich. "Supplemental Notes: GAL22V10 Programming". Electrical Engineering Laboratory I/II. University of Texas, Pan-American. http://faculty.utpa.edu/hfoltz/.../LAB1_Extra_GAL22V10_Programming.pdf. Retrieved 12 January 2014.[yes|permanent dead link|dead link}}]
- ↑ 2.0 2.1 Reeder, Nick. "Programming a GAL22V10". EET1131 Digital Electronics. Sinclair Community College. Archived from the original on 20 February 2014. https://web.archive.org/web/20140220060159/http://people.sinclair.edu/nickreeder/eet1131/programmingGAL.htm. Retrieved 12 December 2013.
- ↑ 3.0 3.1 Dueck, Robert K. (2005). Digital design with CPLD applications and VHDL (2nd ed.). Clifton Park, N.Y. ; [Canada]: Thomson/Delmar Learning. pp. 467–469. ISBN 1401840302.
- ↑ Wirth, N.. "The Programmable Logic Device ispGAL22V10 [sic"]. Institute of Computer Systems, Swiss Federal Institute of Technology, Zurich. http://www.cs.inf.ethz.ch/lola/gal22v10/. Retrieved 12 January 2014.
- ↑ "GAL22V10 Datasheet". Massachusetts Institute of Technology. http://web.mit.edu/6.115/www/document/gal22v10.pdf. Retrieved 6 December 2015.
- ↑ "PCN09I-10". Lattice Semiconductor. http://www.latticesemi.com/dynamic/view_document.cfm?document_id=37118. Retrieved 13 December 2013.
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