Engineering:MCST-R1000

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MCST R1000
MCST-4R FPGA prototype.gif
MCST R1000 FPGA prototype
General Info
Launched2010; 14 years ago (2010)[1]
Designed byMCST
Common manufacturer(s)
Performance
Max. CPU clock rate750 MHz to 1 GHz
FSB speeds2 Gbps
Cache
L1 cache48 KB
L2 cache2 MB
Architecture and classification
ApplicationEmbedded
Min. feature size100 mm²
Instruction setSPARC V9
Physical specifications
Cores
  • 4
Package(s)
  • FPGA
History
PredecessorMCST-R500S
SuccessorMCST-R2000

The MCST R1000 (Russian: МЦСТ R1000) is a 64-bit microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC.[2]

During development this microprocessor was designated as MCST-4R.[1]

MCST R1000 Highlights

  • implements the SPARC V9 instruction set architecture (ISA)
  • quad-core
  • core specifications:
    • in-order, dual-issue superscalar
    • 7-stage integer pipeline
    • 9-stage floating-point pipeline
    • VIS extensions 1 and 2
    • Multiply–accumulate unit
    • 16 KB L1 instruction cache (parity protection)
    • 32 KB L1 data cache (parity protection)
    • size 7.6 mm2
  • shared 2MB L2 cache (ECC protection)
  • integrated memory controller
  • integrated ccNUMA controller
  • 1 GHz clock rate
  • 90 nm process
  • die size 128 mm2
  • ~150 million transistors
  • power consumption 15W
MCST R1000 core
MCST R1000 pipeline MCST R1000 diagram
ccNUMA multiprocessor system with four MCST R1000 microprocessors

References