Engineering:MCST-R2000
From HandWiki
| General Info | |
|---|---|
| Launched | 2018 |
| Designed by | MCST |
| Common manufacturer(s) | |
| Performance | |
| Max. CPU clock rate | 2 GHz |
| Architecture and classification | |
| Instruction set | SPARC V9 |
| Physical specifications | |
| Cores |
|
| History | |
| Predecessor | MCST-R1000 |
The MCST R2000, (e90), (Russian: МЦСТ R2000) is a 64-bit microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC.[1][2]
MCST R2000 Highlights
- implements the SPARC V9 instruction set architecture (ISA)
- octa-core
- core specifications:
- out-of-order, dual-issue superscalar[3]
- two integer units
- one floating-point unit
- out-of-order, dual-issue superscalar[3]
- integrated memory controller
- integrated ccNUMA controller
- 2 GHz clock rate
- 28 nm process
- ~500 million transistors
References
- ↑ "Создатели "Эльбрусов" выпускают процессор альтернативной архитектуры впервые за семь лет". http://www.cnews.ru/news/top/2018-04-27_razrabotchiki_elbrusov_vpervye_za_sem_let.
- ↑ "Показан новый российский 8-ядерный 28-нм процессор МЦСТ R-2000" (in ru). 2018-04-17. http://tehnoomsk.ru/node/3148.
- ↑ (in Russian) Разработка генератора тестов для верификации механизма «байпас» в конвейере микропроцессора МЦСТ R2000, MCST, http://mcst.ru/files/57d66d/280cd8/504173/000000/cherepanov_s.p._razrabotka_generatora_testov_dlya_verifikatsii_mehanizma_baypas_v_konveyere_mikroprotsessora_mtsst_r2000.pdf, retrieved 2019-07-13
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