Engineering:Nord-100
| Developer | Norsk Data |
|---|---|
| Manufacturer | Norsk Data |
| Product family | Nord |
| Type | Minicomputer |
| Generation | 4 |
| Release date | 1979 |
| Lifespan | 1979–198? |
| Operating system | Sintran III |
| CPU | 16-bit |
| Camera | none |
| Touchpad | none |
| Predecessor | Nord-10 |
| Successor | ND-500? |
| Website | example |
The Nord-100 was a 16-bit minicomputer series made by Norsk Data, introduced in 1979. It shipped with the Sintran III operating system, and the architecture was based on, and backward compatible with, the Nord-10 line.
The Nord-100 was originally named the Nord-10/M (M for Micro) as a bit sliced[1] OEM processor. The board was laid out, finished, and tested when they realized that the central processing unit (CPU) was far faster than the Nord-10/S. The result was that all the marketing material for the new NORD-10/M was discarded, the board was rechristened the Nord-100, and extensively advertised as the successor of the Nord-10 line. Later, in an effort to internationalize their line, the machine was renamed ND-100.
Performance
| ND-100 | ND-100/CE | ND-110 | ND-110/CX | ND-120/CX | ND-125/CX | |
|---|---|---|---|---|---|---|
| Minimum number of microinstructions per instruction | 3[citation needed] | 3 | 1[citation needed] | 1 | ||
| Minimum microinstruction cycle time | 150ns[citation needed] | 150ns | 100ns[citation needed] | 100ns | ||
| Whetstone MWIPS | 0.5[citation needed] | 0.5 | 0.3[citation needed] | 0.3 |
CPU
The ND-100 line used a custom processor, and like the PDP-11 line, the CPU decided the name of the computer.
- Nord-100/CE, Commercial Extended, with decimal arithmetic instructions (The decimal instruction set was later renamed CX)
- ND-110, incrementally improved ND-100
- ND-110/CX, an ND-110 with decimal instructions
- ND-120/CX, full redesign
The ND-100 line was machine-instruction compatible with the Nord-10 line, except for some extended instructions, all in supervisor mode, mostly used by the operating system. Like most processors of its time, the native bit grouping was octal, despite the 16-bit word length.
The ND-100 series had a microcoded CPU, with downloadable microcode,[1] and was considered a complex instruction set computer (CISC) processor.
ND-100
The ND-100 was implemented using medium-scale integration (MSI) logic and bit-slice processors.[1]
The ND-100 was frequently sold together with a memory management unit card, the MMS.[1] The combined power use of these boards was 90 watts. The boards would usually occupy slots 2 and 3, for the CPU and MMS, respectively. Slot 1 was reserved for the Tracer, a hardware debugger system.
ND-100/CE
The CE stood for Commercial Extended. The processor was upgraded by replacing the microcode PROM.
It added instruction for decimal arithmetic and conversion, stack instructions, segment-change instructions used by the OS, a block move, test-and-set, and a read-without-cache instruction.
ND-110
The ND-110 was an incremental improvement over the ND-100.
The ND-110 combined the memory management system and CPU, formerly separate cards, on one board. The single CPU/MMS board was plugged into the memory management board slot, usually numbered 3. Power consumption was reduced from 90 watts to 60.
The ND-110 made extensive use of Programmable Array Logic (PALs) and gate arrays, with semi-custom Very Large Scale Integration (VLSI) chips.
The ND-110 had three gate arrays:
- The Micro Instruction Controller, the MIC, also known as RMIC, for Rask MIC (Speedy MIC). It replaced three 74S482 sequencers and about 30 other ICs.
- The Arithmetical and Logical Unit gate array (ALU, also known as the BUFALU). Replaced four Am2901 bit-slice processors, and some added registers like the data bus register the general purpose register, and the internal register block.
- The Micro Address Controller (The MAC, also called RMAC, for Rask MAC (Speedy MAC). It implemented hardware address arithmetic, which in the ND-100 had been done in microcode.
Along with the macro-instruction cache memory also in the ND-100, the ND-110 had a unique implementation of cache memory on the micro-instruction level. The step termed mapping in the ND-100 was then avoided because the first micro-instruction word of a macro-instruction was written into the control store cache.
Unlike the ND-100 CPU, it handled synchronous interrupts as traps, similar to how it was handled by the ND-500.
The control store consisted of 4K x 4 bit 40ns static random-access memory (SRAM) chips. This meant that the control store was writable. It was loaded at power up and Master Clear from two 32Kx8 bit erasable programmable read-only memory (EPROM) units.
The CPU clock and the bus arbitration network were implemented using 15ns PALs.
The main oscillator was a 39.3216 MHz crystal oscillator.
ND-110/CX
This was the ND-110 with the CX microcode programmable read-only memory (PROM). The added instructions were the same as the /CE.
ND-120/CX
The ND-120 CPU was a complete reimplementation on an LSI chip (The so-called Delilah chip), and was originally intended to be sold as the ND-1000, to reflect the technology change, which paralleled the change from the ND-500 series to the ND-5000 (codenamed Samson).
The Samson/Delilah naming scheme may reflect that around the time of the development of the ND-120, it was increasingly clear that the mixed 16/32-bit architecture was a bottleneck for the ND-500(0) architecture; Internal technical documentation used at Norsk Data for the Delilah chip has a drawing of a grinning woman with hair in her clenched fist.
References
External links
- ND-100 Reference Manual. Norsk Data. 1984. ND.06.014.02 Revision A. http://bitsavers.org/pdf/norskData/ND-100-RM-ND-06.014.02_ND-100_Reference_Manual_1984.pdf.
- NORD-100 Input/Output System. Norsk Data. 1980. ND.06.016.01. http://bitsavers.org/pdf/norskData/ND-100-IO-ND-06.016.01_NORD-100_Input_Output_System_1980.pdf.
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