Engineering:Selective area epitaxy
Selective area epitaxy is the local growth of epitaxial layer through a patterned amorphous dielectric mask (typically SiO2 or Si3N4) deposited on a semiconductor substrate. Semiconductor growth conditions are selected to ensure epitaxial growth on the exposed substrate, but not on the dielectric mask.[1] SAE can be executed in various epitaxial growth methods such as molecular beam epitaxy[2] (MBE), metalorganic vapour phase epitaxy (MOVPE)[1] and chemical beam epitaxy (CBE).[3] By SAE, semiconductor nanostructures such as quantum dots and nanowires can be grown to their designed places.[2]
Concepts
Mask
The mask used in SAE is usually amorphous dielectric such as SiO2 or SiN4 which is deposited on the semiconductor substrate. The patterns (holes) in the mask are fabricated using standard microfabrication techniques lithography and etching. Variety of lithography and etching techniques can be implemented to SAE mask fabrication. Suitable techniques depend on the pattern feature size and used materials. Electron beam lithography is widely used due to its nanometer resolution. The mask should withstand the high temperature growth conditions of semiconductors in order to limit the growth to the patterned holes in the mask. [4]
Selectivity
Selectivity in SAE is used to express the growth on the mask. The selectivity of the growth is originated from the property that atoms doesn't favor sticking to the mask i.e. they have low sticking coefficient. Sticking coefficient can be reduced by the choice of mask material, having lower material flow and having higher growth temperature. High selectivity i.e. no growth on the mask is desired. [5]
Growth mechanism
Epitaxial growth mechanism in SAE can be divided in to two parts: Growth before the mask level and growth after the mask level.
Growth before mask level
Before the mask level, the growth is confined to occur only in the hole in the mask. The growth starts to exceed the crystal of the substrate crystal following the pattern of the mask. The grown semiconductor has the structure of the pattern. This is employed in template assisted selective area epitaxy (TASE), where deep patterns in the mask are used as a template for the whole semiconductor structure and the growth is stopped before the mask level. [6]
Growth after the mask level
After the mask level, the growth can exceed to any direction, because the mask is no longer limiting the growth direction. The growth continues to the direction which is energetically favorable for crystal to expand in existing growth conditions. The growth is referred as faceted growth, because it is favorable for crystal to form facets. Therefore, in SAE grown semiconductor structures, clear crystalline facets are seen. The growth direction, or more precisely, the growth rates of different crystal facets can be tuned. Growth temperature, V/III ratio, orientation of the pattern and shape of the pattern are properties that affect to the growth rates of facets. By adjusting these properties, the structure of grown semiconductor can be engineered. SAE grown nanowires and epitaxial lateral overgrown structures (ELO) are an example of structures that are engineered by SAE growth conditions. In nanowire growth, the growth rate of lateral facets is suppressed and the structure grows only in vertical direction.[4] In ELO, the growth is initiated in the mask openings, and after mask level the growth proceeds laterally on the mask, eventually joining the grown semiconductor structures together. The main principle in ELO is to reduce the defects caused by lattice mismatch of the substrate and the grown semiconductor.[7]
Factors that affect to SAE
- Temperature of growth
- V/III ratio
- Choice of mask material
- Orientation of window
- Mask to window ratio
- Quality of mask
- Shape of the pattern
Techniques
SAE can be achieved in various epitaxial growth techniques, which are listed below.
- Metalorganic vapour-phase epitaxy
- Molecular beam epitaxy
- Chemical beam epitaxy
- Liquid phase epitaxy
Applications
- Nanowires
- Quantum dots
- III/V-Silicon integration
- Topological quantum computer
References
- ↑ 1.0 1.1 Stringfellow, Gerald B. (2014). Organometallic Vapor-Phase Epitaxy : Theory and Practice.. Elsevier Science. ISBN 978-0-08-053818-1. OCLC 1056079789.
- ↑ 2.0 2.1 Asahi, Hajime Herausgeber. Horikoshi, Yoshiji Herausgeber. (15 April 2019). Molecular Beam Epitaxy : materials and applications for electronics and optoelectronics. ISBN 978-1-119-35501-4. OCLC 1099903600.
- ↑ Davies, G.J.; Skevington, P.J.; French, C.L.; Foord, J.S. (May 1992). "Selective area growth of III–V compound semiconductors by chemical beam epitaxy". Journal of Crystal Growth 120 (1–4): 369–375. doi:10.1016/0022-0248(92)90420-n. ISSN 0022-0248. Bibcode: 1992JCrGr.120..369D.
- ↑ 4.0 4.1 Shape Engineering of InP Nanostructures by Selective Area Epitaxy. doi:10.1021/acsnano.9b02985.s001. https://figshare.com/articles/journal_contribution/8276879.
- ↑ Van Caenegem, Tom; Moerman, Ingrid; Demeester, Piet (January 1997). "Selective area growth on planar masked InP substrates by metal organic vapour phase epitaxy (MOVPE)". Progress in Crystal Growth and Characterization of Materials 35 (2–4): 263–288. doi:10.1016/s0960-8974(98)00003-5. ISSN 0960-8974.
- ↑ Schmid, H.; Borg, M.; Moselund, K.; Cutaia, D.; Riel, H. (2015-09-29). "(Invited) Template-Assisted Selective Epitaxy (TASE) of III-V Nanoscale Devices for Heterogeneous Integration with Si". Extended Abstracts of the 2015 International Conference on Solid State Devices and Materials (The Japan Society of Applied Physics). doi:10.7567/ssdm.2015.d-4-1.
- ↑ Olsson, F.; Xie, M.; Lourdudoss, S.; Prieto, I.; Postigo, P. A. (November 2008). "Epitaxial lateral overgrowth of InP on Si from nano-openings: Theoretical and experimental indication for defect filtering throughout the grown layer". Journal of Applied Physics 104 (9): 093112–093112–6. doi:10.1063/1.2977754. ISSN 0021-8979. Bibcode: 2008JAP...104i3112O.
 |  |
