Interrupt vector table
An interrupt vector table (IVT) is a data structure that associates a list of interrupt handlers with a list of interrupt requests in a table of interrupt vectors. Each entry of the interrupt vector table, called an interrupt vector, is the address of an interrupt handler (also known as ISR). While the concept is common across processor architectures, IVTs may be implemented in architecture-specific fashions. For example, a dispatch table is one method of implementing an interrupt vector table.
Interrupts are assigned a number between 0 to 255. The interrupt vectors for each interrupt number are stored in the lower 1024 bytes of main memory. For example, interrupt 0 is stored from 0000:0000 to 0000:0003, interrupt 1 from 0000:0004 to 0000:0007, and so on.
| Interrupt Number | IVT Address | Interrupt Name |
|---|---|---|
| 0 | 00-03 | CPU divide by zero |
| 1 | 04-07 | Debug single step |
| 2 | 08-0B | Non Maskable Interrupt (NMI input on processor) |
| 3 | 0C-0F | Debug breakpoints |
| 4 | 10-13 | Arithmetic overflow |
| 5 | 14-17 | BIOS provided Print Screen routine |
| 6 | 18-1B | Reserved |
| 7 | 1C-1F | Reserved |
| 8 | 20-23 | IRQ0, Time of day hardware services |
| 9 | 24-27 | IRQ1, Keyboard Interface |
| A | 28-2B | IRQ2, ISA Bus cascade services for second 8259 |
| B | 2C-2F | IRQ3, Com 2 hardware |
| C | 30-33 | IRQ4, Com1 hardware |
| D | 34-37 | IRQ5, LPT2, Parallel port hardware (Hard Disk on XT) |
| E | 38-3B | IRQ6, Floppy Disk adaptor |
| F | 3C-3F | IRQ7, LPT1, Parallel port hardware |
| 10 | 40-43 | Video services, see note 1 |
| 11 | 44-47 | Equipment check |
| 12 | 48-4B | Memory size determination |
| 13 | 4C-4F | Floppy I/O routines |
| 14 | 50-53 | Serial port I/O routines |
| 15 | 54-57 | PC used for Cassette tape services |
| 16 | 58-5B | Keyboard I/O routines |
| 17 | 5C-5F | Printer I/O routines |
| 18 | 60-63 | Points to basic interpreter in a "real" IBM PC |
| 19 | 64-67 | Bootstrap loader |
| 1A | 68-6B | Time of day services |
| 1B | 6C-6F | Services Ctrl-Break service |
| 1C | 70-73 | Timer tick (provides 18.2 ticks per second) |
| 1D | 74-77 | Video parameters |
| 1E | 78-7B | Disk parameters |
| 1F | 7C-7F | Video graphics |
| 20 | 80-83 | Program termination (obsolete) |
| 21 | 84-87 | All DOS services available through this Interrupt |
| 22 | 88-8B | Terminate address |
| 23 | 8C-8F | Ctrl-Break exit address |
| 24 | 90-93 | Critical error handler |
| 25 | 94-97 | Read logical sectors |
| 26 | 98-9B | Write logical sectors |
| 27 | 9C-9F | Terminate and stay resident routines (obsolete) |
| 28 to 3F | A0-A3 to FC-FF | Reserved for DOS |
| 40 to 4F | 100-103 to 13C-13F | Reserved for BIOS |
| 50 | 140-143 | Reserved for BIOS |
| 51 | 144-147 | Mouse functions |
| 52 to 59 | 148-14B to 164-167 | Reserved for BIOS |
| 5A | 168-16B | Reserved for BIOS |
Background
Most processors have an interrupt vector table, including chips from Intel, AMD, Infineon, Microchip[1] Atmel,[2] NXP, ARM[3][4] etc.
Interrupt handlers
Handling methods
An interrupt vector table is used in the three most popular methods of finding the starting address of the interrupt service routine:
"Predefined"
The "predefined" method loads the program counter (PC) directly with the address of some entry inside the interrupt vector table. The jump table itself contains executable code. While in principle an extremely short interrupt handler could be stored entirely inside the interrupt vector table, in practice the code at each entry is a single jump instruction that jumps to the full interrupt service routine (ISR) for that interrupt. The Intel 8080,[5] Atmel AVR[6][7] and all 8051 and Microchip microcontrollers[8] use the predefined approach.
"Fetch"
The "fetch" method loads the PC indirectly, using the address of some entry inside the interrupt vector table to pull an address out of that table, and then loading the PC with that address.[8] Each and every entry of the IVT is the address of an interrupt service routine. All Motorola/Freescale microcontrollers use the fetch method.[8]
"Interrupt acknowledge"
For the "interrupt acknowledge" method, the external device gives the CPU an interrupt handler number. The interrupt acknowledge method is used by the Intel Pentium and many older microprocessors.[8]
When the CPU is affected by an interrupt, it looks up the interrupt handler in the interrupt vector table, and transfers control to it.
See also
- Interrupt descriptor table (x86 Architecture implementation)
References
- ↑ "dsPIC33F Family Reference Manual" section 29.1.1 Interrupt Vector Table
- ↑ "AVR Libc User Manual" section: Introduction to avr-libc's interrupt handling
- ↑ "Documentation – Arm Developer". https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-processor/exception-model/vector-table.
- ↑ "Documentation – Arm Developer – AArch64 exception vector table". https://developer.arm.com/documentation/100933/0100/AArch64-exception-vector-table?lang=en.
- ↑ Intel 8080 Microcomputer Systems User's Manual. Intel Corporation. September 1975. pp. 2–11 Interrupt Sequences. OCLC 2058546.
- ↑ Roger L. Traylor. "Interrupts: AVR interrupt servicing"
- ↑ Gary Hill. "Atmel AVR Interrupt and Timing Subsystems: ATMEGA328P interrupt vector table"
- ↑ 8.0 8.1 8.2 8.3 Huang, Han-Wat (2005). Pic Microcontroller: An Introduction to Software and Hardware Interfacing. Cengage Learning. p. 247. ISBN 978-1-4018-3967-3. https://books.google.com/books?id=CB9GaAU1dwsC&pg=PA247. Retrieved 22 April 2013.
External links
- Intel® Architecture Software Developer's Manual, Volume 3: System Programming Guide
- Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:System Programming Guide, Part 1 (see CHAPTER 6, INTERRUPT AND EXCEPTION HANDLING and CHAPTER 10, ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER)]
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