LowRISC

From HandWiki
lowRISC C.I.C.
TypeCommunity Interest Company
FoundedOctober 20, 2014; 11 years ago (2014-10-20) in Cambridge, UK
FoundersGavin Ferris, Alex Bradbury, Robert Mullins
Headquarters
Cambridge
,
United Kingdom
ProductsIbex, OpenTitan
Website{{{1}}}

lowRISC C.I.C. is a not-for-profit company headquartered in Cambridge, UK. It uses collaborative engineering to develop and maintain open source silicon designs and tools.[1] lowRISC is active in RISC-V-related open source hardware and software development and stewards the OpenTitan project.

Projects

OpenTitan

OpenTitan is the first open source silicon Root of Trust (RoT) project.[2] It is designed to be integrated into data center servers, storage devices, peripherals and other hardware.[3] OpenTitan is under the stewardship of lowRISC and collaboratively developed by Google, ETH Zurich, Nuvoton, G+D Mobile Security, Seagate, and Western Digital.[4] The OpenTitan source code is available on GitHub, released under the permissive Apache 2 license.

Ibex CPU core

Ibex is an embedded open source 32-bit in-order RISC-V CPU core, which has been taped out multiple times.[5] Ibex is used in the OpenTitan chip. Development on Ibex started in 2015 under the name "Zero-riscy" and "Micro-riscy" at the ETH Zurich and University of Bologna, where it was part of the PULP platform. In December 2018 lowRISC took over the development.[6] Luca Benini of the ETH Zurich sits on lowRISC' board.

Prototype 64-bit SoC design

The lowRISC prototype 64-bit SoC design is an open source Linux-capable 64-bit RISC-V SoC design. A first version preview release of the source code was made available in April 2015.[7] Since then features were added, such as support for tagged memory and "minion cores", small CPU cores which are dedicated to I/O tasks.[8] The latest version 0.6 was released in November 2018,[9] and is available to download and try out on an FPGA.

Other projects

lowRISC initiated and led the upstreaming of the RISC-V LLVM backend, where Alex Bradbury is code owner.[10]

Governance

lowRISC's governance and current appointed directors are set out in its entry at the UK Companies House.[11]

History

lowRISC was spun out of the University of Cambridge Computer Lab in 2014[12] by Alex Bradbury, Robert Mullins, and Gavin Ferris with the goal of creating a fully open source SoC and low-cost development board.[13][14]

In 2015 lowRISC became one of the founding members of the RISC-V Foundation (today: RISC-V International).[15]

Since 2018 lowRISC has been focusing on collaborative engineering with partner organizations. In 2019 the OpenTitan project, stewarded by lowRISC, was announced.[16]

References

  1. ↑ "What is lowRISC? - lowRISC". lowRISC. https://lowrisc.org/lowrisc/. 
  2. ↑ Anderson, Tim (5 Nov 2019). "Cambridge boffins and Google unveil open-source OpenTitan chip – because you never know who you can trust". The Register. https://www.theregister.com/2019/11/05/google_opentitan_soc_riscv/. 
  3. ↑ "Open source silicon Root of Trust". https://opentitan.org. 
  4. ↑ "OpenTitan partners". https://opentitan.org/#partners. 
  5. ↑ "Ibex: An embedded 32 bit RISC-V CPU core". https://ibex-core.readthedocs.io/en/latest/index.html. 
  6. ↑ "Ibex Reference Guide: History". https://ibex-core.readthedocs.io/en/latest/03_reference/history.html. 
  7. ↑ "lowRISC tagged memory preview release". April 13, 2015. https://www.lowrisc.org/blog/2015/04/lowrisc-tagged-memory-preview-release/. 
  8. ↑ "Overview of the minion infrastructure". https://www.lowrisc.org/docs/minion-v0.4/overview/. 
  9. ↑ "lowRISC 0-6 milestone release". 2018-11-12. https://www.lowrisc.org/blog/2018/11/lowrisc-0-6-milestone-release. 
  10. ↑ Bradbury, Alex. "The RISC-V LLVM backend in Clang/LLVM 9.0". https://www.lowrisc.org/blog/2019/07/risc-v-llvm-backend-in-clang-llvm-9.0/. 
  11. ↑ lowRISC entry on the Companies House website
  12. ↑ "History - lowRISC". lowRISC. https://lowrisc.org/history/. 
  13. ↑ "Free Core, Some Assembly Required". EETimes. 2016-01-07. https://www.eetimes.com/free-core-some-assembly-required/. 
  14. ↑ "LowRISC SoC - 1st RISC-V Workshop". https://www.youtube.com/watch?v=r1i9SAOdyS4. 
  15. ↑ "Founding Members". https://riscv.org/membership/founding-members/. 
  16. ↑ Bradbury, Alex (2019-11-05). "Announcing OpenTitan, the First Transparent Silicon Root of Trust". https://www.lowrisc.org/blog/2019/11/announcing-opentitan-the-first-transparent-silicon-root-of-trust/. 
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