Physics:Magneto-electric spin-orbit

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Short description: Technology designed for constructing scalable integrated circuits

Magneto-electric spin-orbit (MESO) is a technology designed for constructing scalable integrated circuits, that works with a different operating principle than CMOS devices such as MOSFETs, proposed by Intel,[1] that is compatible with CMOS device manufacturing techniques and machinery.[2][3]

MESO devices operate by the coupling of the magnetoelectric effect with the spin orbit coupling.[3] Specifically, the magnetoelectric effect will induce a change in magnetization within the device due to an induced electric field, which can then be read out by the spin orbit coupling component which converts it into an electric charge.[4][3] This mechanism is analogous to how a CMOS device operates with the source, gate and drain electrodes working together to form a logic gate.

As of 2020, the technology is under development by Intel and University of California, Berkeley.[5] The first experiment, conducted in 2020 in nanoGUNE, proved that spin-orbit coupling could be used for implementing MESO.[6]

Performance

Before the introduction of MESO, Intel evaluated 17 different device architectures for beyond CMOS scaling which aims to circumvent scaling challenges present with CMOS devices such as MOSFETs used in integrated circuits. For testing, these architectures were made with production processes compatible with those used for CMOS devices since some CMOS devices are still necessary for interfacing with other circuits and for providing the clock signal for an integrated circuit, and for reusing existing production equipment: Tunneling FETs, graphene p-n junctions, ITFETs, BisFET, spinFETs, all spin logic, spin torque oscillators, domain wall logic, spin torque majority, spin torque triad, spin wave device, nano magnet logic, charge spin logic, piezo FETs, MITFETs, FeFETs and negative capacitance FETs were tested and it was found that none offered both improved performance characteristics and lower power consumption compared with CMOS. According to VentureBeat, simulations showed that, on a 32-bit ALU, MESO devices offer both higher performance (processing speed in TOPS per cm2) and lower power density than CMOS HP devices, which had the highest performance among all other devices except MESO.[7][2]

Compared to CMOS, MESO circuits can require less energy for switching, can have a lower operating voltage, feature a higher integration density, possess non-volatility which allows for ultra low standby power consumption, and the energy required to switch MESO devices scales down cubically with every miniaturization by a factor of two of the device.[3] These features make MESO attractive for replacing CMOS devices in the design of future logic gates and circuits in integrated circuits as it can help increase their performance and lower their power consumption.

There is a huge challenge in the ME writing processes regarding the necessary materials. In recent years, great efforts are being made in the scientific community in order to make the magnetoelectric effects work in nanostructure (thin film). The main issue is that, when ferroelectric material transfers to thinfilm, it loses its FE properties, making it even more difficult to achieve a high efficiency-coupling of FE-FM (ME) at nanometer-size systems.

Feature Size [nm][3] Supply Voltage [mV][3] Switching Energy [J][3]
CMOS 10 100 - 700 300x10−18
MESO 10 10 - 100 10x10−18

References

  1. ↑ https://www.extremetech.com/computing/286163-intels-fundamentally-new-meso-architecture-could-arrive-in-a-few-years
  2. ↑ 2.0 2.1 "Intel looks beyond CMOS to MESO". 14 January 2022. https://venturebeat.com/technology/intel-looks-beyond-cmos-to-meso/. 
  3. ↑ 3.0 3.1 3.2 3.3 3.4 3.5 3.6 Manipatruni, Sasikanth; Nikonov, Dmitri E.; Lin, Chia-Ching; Gosavi, Tanay A.; Liu, Huichu; Prasad, Bhagwati; Huang, Yen-Lin; Bonturim, Everton et al. (2018). "Scalable energy-efficient magnetoelectric spin–orbit logic". Nature 565 (7737): 35–42. doi:10.1038/s41586-018-0770-2. PMID 30510160. 
  4. ↑ Lin, Chia-Ching; Gosavi, Tanay; Nikonov, Dmitri E.; Huang, Yen-Lin; Prasad, Bhagwati; Choi, WonYoung; Pham, Van Tuong; Groen, Inge et al. (2019). "Experimental demonstration of integrated magneto-electric and spin-orbit building blocks implementing energy-efficient logic". 2019 IEEE International Electron Devices Meeting (IEDM). 37.3.1–37.3.4. doi:10.1109/IEDM19573.2019.8993620. ISBN 978-1-7281-4032-2. 
  5. ↑ "How the New Quantum 'MESO' Architecture Could Replace CMOS". DesignNews. 10 January 2019. https://www.designnews.com/electronics-test/how-new-quantum-meso-architecture-could-replace-cmos/52879693360067?ADTRK=UBM&elq_mid=7186&elq_cid=889505. 
  6. ↑ Pham, Van Tuong; Groen, Inge; Manipatruni, Sasikanth; Choi, Won Young; Nikonov, Dmitri E.; Sagasta, Edurne; Lin, Chia-Ching; Gosavi, Tanay A. et al. (June 2020). "Spin–orbit magnetic state readout in scaled ferromagnetic/heavy metal nanostructures" (in en). Nature Electronics 3 (6): 309–315. doi:10.1038/s41928-020-0395-y. ISSN 2520-1131. http://www.nature.com/articles/s41928-020-0395-y. 
  7. ↑ https://www.eetimes.com/intel-shows-life-beyond-cmos/




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