From HandWiki

SigmaQuad - Quad Data Rate SRAM is a type of static RAM computer memory that can transfer up to four words of data in each clock cycle. Like Double Data-Rate (DDR) SDRAM, SigmaQuad SRAM transfers data on both rising and falling edges of the clock signal. This requires more wires between the memory device and the memory controller, but doubles the theoretical maximum data transfer rate. SigmaQuad SRAM uses two clocks, one for read data and one for write data. This helps to eliminate problems caused by the propagation delay of the clock wiring, and allows concurrent reads and writes, thereby doubling the transfer rate again.

SigmaQuad SRAM was designed for high-speed communications and networking applications, where data throughput is more important than cost, power efficiency or density. The technology was a joint development by GSI Technology, Sony Microelectronics and ISSI.

Contents [hide]

Clock Inputs


  1. Input clock: K, /K
  2. Output clock: C, /C

Control Inputs

Control Lines:

  1. not-Write enable: /WPS
  2. not-Read enable: /RPS


Address and Data Buses:

  1. Address bus
  2. Data in bus
  3. Data out bus

Clocking scheme

Address Clock

  1. Read address latched on rising edge of K
  2. Write address latched on rising edge of K

Write Data Clock If /WPS is low

  1. A data word on Data In is latched on rising edge of K
  2. The next data word on Data In is latched on rising edge of /K

Read Data Clock A read is a two-cycle process

  1. If /RPS is low
  2. The first rising edge of K latches the read address, A
  3. The second rising edge of K puts the data word, from address A, on the Data Out bus
  4. The next rising edge of /K puts the next data word, from address A+1, on the Data Out bus