Engineering:WIMG (CPU)

WIMG is an acronym that describes that memory/cache attributes for PowerPC/Power ISA. Each letter of WIMG represents a one bit access attribute, specifically: Write-Through Access (W), Cache-Inhibited Access (I), Memory Coherence (M), and Guarded (G).

Write-Through Access (W)

When set to 1, indicates a Write-Through Access. When set to 0 indicates access to address that is non-Write Through.

Cache-Inhibited Access (I)

When set to 1, indicates a Cache-Inhibited Access. When set to 0 indicates access to address that is cacheable. External caches such as look-aside and directory protocols use this bit to determine their actions. The value of the I bit must be same for all accesses by processors to a given address carried by the Ax() field.1 However, an I/O or peripheral may access with I bit set to 1 an address that is being accessed by processors with I bit set to 0. Such aliasing of the I bit is not considered an error. The combination W=I=1 is not supported.

Memory Coherence (M)

When set to 1, requires that Memory Coherence must be enforced regardless of the values of the other qualifiers. Specifically, the cache hierarchies must snoop the transaction even if the I bit is set. If the M bit is not set during the presentation of the transaction to a snooper, the snooper must ignore the transaction. However, the originator of a transaction may not ignore it even if M = 0.

Guarded Writes (G)

All Cache-Inhibited and Guarded Writes (G = 1) issued by a given processor must be performed in the system in the order of their issuance by that processor regardless of the coherency qualifier, and regardless of the addresses carried by the transactions.

See also

• Common Hardware Reference Platform (CHRP)
• List of PowerPC processors
• Power Architecture Platform Reference (PAPR)
• PowerOpen Environment
• PowerPC Reference Platform (PReP)
• RTEMS real-time operating system

References

• PowerPC Architecture History Diagram

External links

• PPC Overview - an overview of PowerPC processors
• OS/2 Warp, PowerPC Edition review by Michal Necasek 2005
• PowerPC Architecture History Diagram