PowerPC

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Short description: RISC instruction set architecture by AIM alliance
PowerPC
PowerPC logo.svg
DesignerAIM
Bits32-bit/64-bit (32 → 64)
IntroducedOctober 1992; 31 years ago (1992-10)
Version2.02[1]
DesignRISC
TypeLoad–store
EncodingFixed/Variable (Book E)
BranchingCondition code
EndiannessBig/Bi
ExtensionsAltiVec, PowerPC-AS, APU
Registers
General purpose32
Floating point32
Vector32 (with AltiVec)
IBM PowerPC 601 microprocessor

PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple–IBM–Motorola alliance, known as AIM. PowerPC, as an evolving instruction set, has been named Power ISA since 2006, while the old name lives on as a trademark for some implementations of Power Architecture–based processors.

PowerPC was the cornerstone of AIM's PReP and Common Hardware Reference Platform (CHRP) initiatives in the 1990s. Originally intended for personal computers, the architecture is well known for being used by Apple's Power Macintosh, PowerBook, iMac, iBook, eMac, and Xserve lines from 1994 until 2005, when Apple migrated to Intel's x86. It has since become a niche in personal computers, but remains popular for embedded and high-performance processors. Its use in 7th generation of video game consoles and embedded applications provide an array of uses, including satellites, and the Curiosity and Perseverance rovers on Mars. In addition, PowerPC CPUs are still used in AmigaOne and third party AmigaOS 4 personal computers.

PowerPC is largely based on the earlier IBM POWER architecture, and retains a high level of compatibility with it; the architectures have remained close enough that the same programs and operating systems will run on both if some care is taken in preparation; newer chips in the Power series use the Power ISA.

History

The history of RISC began with IBM's 801 research project, on which John Cocke was the lead developer, where he developed the concepts of RISC in 1975–78. 801-based microprocessors were used in a number of IBM embedded products, eventually becoming the 16-register IBM ROMP processor used in the IBM RT PC. The RT PC was a rapid design implementing the RISC architecture. Between the years of 1982 and 1984, IBM started a project to build the fastest microprocessor on the market; this new 32-bit architecture became referred to as the America Project throughout its development cycle, which lasted for approximately 5–6 years. The result is the POWER instruction set architecture, introduced with the RISC System/6000 in early 1990.

The original POWER microprocessor, one of the first superscalar RISC implementations, is a high performance, multi-chip design. IBM soon realized that a single-chip microprocessor was needed in order to scale its RS/6000 line from lower-end to high-end machines. Work began on a one-chip POWER microprocessor, designated the RSC (RISC Single Chip). In early 1991, IBM realized its design could potentially become a high-volume microprocessor used across the industry.

Apple and Motorola involvement

Apple had already realized the limitations and risks of its dependency upon a single CPU vendor at a time when Motorola was falling behind on delivering the 68040 CPU. Furthermore, Apple had conducted its own research and made an experimental quad-core CPU design called Aquarius,[2]:86–90 which convinced the company's technology leadership that the future of computing was in the RISC methodology.[2]:287–288 IBM approached Apple with the goal of collaborating on the development of a family of single-chip microprocessors based on the POWER architecture. Soon after, Apple, being one of Motorola's largest customers of desktop-class microprocessors,[3] asked Motorola to join the discussions due to their long relationship, Motorola having had more extensive experience with manufacturing high-volume microprocessors than IBM, and to form a second source for the microprocessors. This three-way collaboration between Apple, IBM, and Motorola became known as the AIM alliance.

In 1991, the PowerPC was just one facet of a larger alliance among these three companies. At the time, most of the personal computer industry was shipping systems based on the Intel 80386 and 80486 chips, which have a complex instruction set computer (CISC) architecture, and development of the Pentium processor was well underway. The PowerPC chip was one of several joint ventures involving the three alliance members, in their efforts to counter the growing Microsoft-Intel dominance of personal computing.

For Motorola, POWER looked like an unbelievable deal. It allowed the company to sell a widely tested and powerful RISC CPU for little design cash on its own part. It also maintained ties with an important customer, Apple, and seemed to offer the possibility of adding IBM too, which might buy smaller versions from Motorola instead of making its own.

At this point Motorola already had its own RISC design in the form of the 88000, which was doing poorly in the market. Motorola was doing well with its 68000 family and the majority of the funding was focused on this. The 88000 effort was somewhat starved for resources.

The 88000 was already in production, however; Data General was shipping 88000 machines and Apple already had 88000 prototype machines running. The 88000 had also achieved a number of embedded design wins in telecom applications. If the new POWER one-chip version could be made bus-compatible at a hardware level with the 88000, that would allow both Apple and Motorola to bring machines to market far faster since they would not have to redesign their board architecture.

The result of these various requirements is the PowerPC (performance computing) specification. The differences between the earlier POWER instruction set and that of PowerPC is outlined in Appendix E of the manual for PowerPC ISA v.2.02.[1]

Operating systems

Since 1991, IBM had a long-standing desire for a unifying operating system that would simultaneously host all existing operating systems as personalities upon one microkernel. From 1991 to 1995, the company designed and aggressively evangelized what would become Workplace OS, primarily targeting PowerPC.[2]:290–291

When the first PowerPC products reached the market, they were met with enthusiasm. In addition to Apple, both IBM and the Motorola Computer Group offered systems built around the processors. Microsoft released Windows NT 3.51 for the architecture, which was used in Motorola's PowerPC servers, and Sun Microsystems offered a version of its Solaris OS. IBM ported its AIX Unix. Workplace OS featured a new port of OS/2 (with Intel emulation for application compatibility), pending a successful launch of the PowerPC 620. Throughout the mid-1990s, PowerPC processors achieved benchmark test scores that matched or exceeded those of the fastest x86 CPUs.

Ultimately, demand for the new architecture on the desktop never truly materialized. Windows, OS/2, and Sun customers, faced with the lack of application software for the PowerPC, almost universally ignored the chip. IBM's Workplace OS platform (and thus, OS/2 for PowerPC) was summarily canceled upon its first developers' release in December 1995 due to the simultaneous buggy launch of the PowerPC 620. The PowerPC versions of Solaris and Windows were discontinued after only a brief period on the market. Only on the Macintosh, due to Apple's persistence, did the PowerPC gain traction. To Apple, the performance of the PowerPC was a bright spot in the face of increased competition from Windows 95 and Windows NT-based PCs.

With the cancellation of Workplace OS, the general PowerPC platform (especially AIM's Common Hardware Reference Platform) was instead seen as a hardware-only compromise to run many operating systems one at a time upon a single unifying vendor-neutral hardware platform.[2]:287–288

In parallel with the alliance between IBM and Motorola, both companies had development efforts underway internally. The PowerQUICC line was the result of this work inside Motorola. The 4xx series of embedded processors was underway inside IBM. The IBM embedded processor business grew to nearly US$100 million in revenue and attracted hundreds of customers.

The development of the PowerPC is centered at an Austin, Texas, facility called the Somerset Design Center. The building is named after the site in Arthurian legend where warring forces put aside their swords, and members of the three teams that staff the building say the spirit that inspired the name has been a key factor in the project's success thus far.
Part of the culture here is not to have an IBM or Motorola or Apple culture, but to have our own.

Breakup of AIM

A schematic showing the evolution of the different POWER, PowerPC and Power ISAs

Toward the close of the decade, manufacturing issues began plaguing the AIM alliance in much the same way they did Motorola, which consistently pushed back deployments of new processors for Apple and other vendors: first from Motorola in the 1990s with the PowerPC 7xx and 74xx processors, and IBM with the 64-bit PowerPC 970 processor in 2003. In 2004, Motorola exited the chip manufacturing business by spinning off its semiconductor business as an independent company called Freescale Semiconductor. Around the same time, IBM exited the 32-bit embedded processor market by selling its line of PowerPC products to Applied Micro Circuits Corporation (AMCC) and focusing on 64-bit chip designs, while maintaining its commitment of PowerPC CPUs toward game console makers such as Nintendo's GameCube, Wii and Wii U, Sony's PlayStation 3 and Microsoft's Xbox 360, of which the latter two both use 64-bit processors. In 2005, Apple announced they would no longer use PowerPC processors in their Apple Macintosh computers, favoring Intel-produced processors instead, citing the performance limitations of the chip for future personal computer hardware specifically related to heat generation and energy usage, as well as the inability of IBM to move the 970 processor to the 3 GHz range. The IBM-Freescale alliance was replaced by an open standards body called Power.org. Power.org operates under the governance of the IEEE with IBM continuing to use and evolve the PowerPC processor on game consoles and Freescale Semiconductor focusing solely on embedded devices.

IBM continues to develop PowerPC microprocessor cores for use in their application-specific integrated circuit (ASIC) offerings. Many high volume applications embed PowerPC cores.

The PowerPC specification is now handled by Power.org where IBM, Freescale, and AMCC are members. PowerPC, Cell and POWER processors are now jointly marketed as the Power Architecture. Power.org released a unified ISA, combining POWER and PowerPC ISAs into the new Power ISA v.2.03 specification and a new reference platform for servers called PAPR (Power Architecture Platform Reference).

Generations

Many PowerPC designs are named and labeled by their apparent technology generation. That began with the "G3", which was an internal project name inside AIM for the development of what would become the PowerPC 750 family.[4] Apple popularized the term "G3" when they introduced Power Mac G3 and PowerBook G3 at an event at 10 November 1997. Motorola and Apple liked the moniker and used the term "G4" for the 7400 family introduced in 1998[5][6] and the Power Mac G4 in 1999.

At the time the G4 was launched, Motorola categorized all their PowerPC models (former, current and future) according to what generation they adhered to, even renaming the older 603e core "G2". Motorola had a G5 project that never came to fruition, but the name stuck and Apple reused it when the 970 family launched in 2003 even if those were designed and built by IBM.

PowerPC generations according to Motorola, c. 2000.[7]
G1: The 601, 500 and 800 family processors
G2: The 602, 603, 604, 620, 8200 and 5000 families
G3: The 750 and 8300 families
G4: The 7400 and 8400* families
G5: The 7500* and 8500 families (Motorola didn't use the G5 moniker after Apple usurped the name)
G6: The 7600*
(*) These designs didn't become real products.

Design features

POWER, PowerPC, and Power ISA architectures
NXP (formerly Freescale and Motorola)
IBM
IBM/Nintendo
Other
Related links
Cancelled in gray, historic in italic

The PowerPC is designed along RISC principles and allows for a superscalar implementation. Versions of the design exist in both 32-bit and 64-bit implementations. Starting with the basic POWER specification, the PowerPC added:

  • Support for operation in both big-endian and little-endian modes; the PowerPC can switch from one mode to the other at run-time (see below). This feature is not supported in the PowerPC 970.
  • Single-precision forms of some floating-point instructions, in addition to double-precision forms
  • Additional floating-point instructions at the behest of Apple
  • A complete 64-bit specification that is backward compatible with the 32-bit mode
  • A fused multiply–add
  • A paged memory management architecture that is used extensively in server and PC systems.
  • Addition of a new memory management architecture called Book-E, replacing the conventional paged memory management architecture for embedded applications. Book-E is application software compatible with existing PowerPC implementations but needs minor changes to the operating system.

Some instructions present in the POWER instruction set were deemed too complex and were removed in the PowerPC architecture. Some removed instructions could be emulated by the operating system if necessary. The removed instructions are:

  • Conditional moves
  • Load and store instructions for the quad-precision floating-point data type
  • String instructions.

Endian modes

Most PowerPC chips switch endianness via a bit in the MSR (machine state register), with a second bit provided to allow the OS to run with a different endianness. Accesses to the "inverted page table" (a hash table that functions as a TLB with off-chip storage) are always done in big-endian mode. The processor starts in big-endian mode.

In little-endian mode, the three lowest-order bits of the effective address are exclusive-ORed with a three bit value selected by the length of the operand. This is enough to appear fully little-endian to normal software. An operating system will see a warped view of the world when it accesses external chips such as video and network hardware. Fixing this warped view requires that the motherboard perform an unconditional 64-bit byte swap on all data entering or leaving the processor. Endianness thus becomes a property of the motherboard. An OS that operates in little-endian mode on a big-endian motherboard must both swap bytes and undo the exclusive-OR when accessing little-endian chips.

AltiVec operations, despite being 128-bit, are treated as if they were 64-bit. This allows for compatibility with little-endian motherboards that were designed prior to AltiVec.

An interesting side effect of this implementation is that a program can store a 64-bit value (the longest operand format) to memory while in one endian mode, switch modes, and read back the same 64-bit value without seeing a change of byte order. This will not be the case if the motherboard is switched at the same time.

Mercury Systems and Matrox ran the PowerPC in little-endian mode. This was done so that PowerPC devices serving as co-processors on PCI boards could share data structures with host computers based on x86. Both PCI and x86 are little-endian. OS/2 and Windows NT for PowerPC ran the processor in little-endian mode while Solaris, AIX and Linux ran in big endian.[8]

Some of IBM's embedded PowerPC chips use a per-page endianness bit. None of the previous applies to them.

Implementations

IBM PowerPC 604e 200 MHz
Custom PowerPC CPU from the Nintendo Wii video game console
The Freescale XPC855T Service Processor of a Sun Fire V20z

The first implementation of the architecture was the PowerPC 601, released in 1992, based on the RSC, implementing a hybrid of the POWER1 and PowerPC instructions. This allowed the chip to be used by IBM in their existing POWER1-based platforms, although it also meant some slight pain when switching to the 2nd generation "pure" PowerPC designs. Apple continued work on a new line of Macintosh computers based on the chip, and eventually released them as the 601-based Power Macintosh on March 14, 1994.

Accelerator cards based on the first-generation PowerPC chips were created for the Commodore Amiga in anticipation for a move to a possible new Amiga platform designed around the PowerPC. The accelerator cards also included either a Motorola 68040 or 68060 CPU in order to maintain backwards compatibility, as very few apps at the time could run natively on the PPC chips. However, the new machines never materialized, and Commodore subsequently declared bankruptcy. Over a decade later, AmigaOS 4 would be released, which would put the platform permanently on the architecture. OS4 is compatible with those first-generation accelerators, as well as several custom motherboards created for a new incarnation of the Amiga platform.

IBM also had a full line of PowerPC based desktops built and ready to ship; unfortunately, the operating system that IBM had intended to run on these desktops—Microsoft Windows NT—was not complete by early 1993, when the machines were ready for marketing. Accordingly, and further because IBM had developed animosity toward Microsoft, IBM decided to port OS/2 to the PowerPC in the form of Workplace OS. This new software platform spent three years (1992 to 1995) in development and was canceled with the December 1995 developer release, because of the disappointing launch of the PowerPC 620. For this reason, the IBM PowerPC desktops did not ship, although the reference design (codenamed Sandalbow) based on the PowerPC 601 CPU was released as an RS/6000 model (Byte's April 1994 issue included an extensive article about the Apple and IBM PowerPC desktops).

Apple, which also lacked a PowerPC based OS, took a different route. Utilizing the portability platform yielded by the secret Star Trek project, the company ported the essential pieces of their Mac OS operating system to the PowerPC architecture, and further wrote a 68k emulator that could run 68k based applications and the parts of the OS that had not been rewritten.

The second generation was "pure" and includes the "low end" PowerPC 603 and "high end" PowerPC 604. The 603 is notable due to its very low cost and power consumption. This was a deliberate design goal on Motorola's part, who used the 603 project to build the basic core for all future generations of PPC chips. Apple tried to use the 603 in a new laptop design but was unable due to the small 8 KB level 1 cache. The 68000 emulator in the Mac OS could not fit in 8 KB and thus slowed the computer drastically.[9][10] The 603e solved this problem by having a 16 KB L1 cache, which allowed the emulator to run efficiently.

In 1993, developers at IBM's Essex Junction, Burlington, Vermont facility started to work on a version of the PowerPC that would support the Intel x86 instruction set directly on the CPU. While this was just one of several concurrent power architecture projects that IBM was working on, this chip began to be known inside IBM and by the media as the PowerPC 615. Profitability concerns and rumors of performance issues in the switching between the x86 and native PowerPC instruction sets resulted in the project being canceled in 1995 after only a limited number of chips were produced for in-house testing. Aside the rumors, the switching process took only 5 cycles, or the amount of time needed for the processor to empty its instruction pipeline. Microsoft also aided the processor's demise by refusing to support the PowerPC mode.[11]

The first 64-bit implementation is the PowerPC 620, but it appears to have seen little use because Apple didn't want to buy it and because, with its large die area, it was too costly for the embedded market. It was later and slower than promised, and IBM used their own POWER3 design instead, offering no 64-bit "small" version until the late-2002 introduction of the PowerPC 970. The 970 is a 64-bit processor derived from the POWER4 server processor. To create it, the POWER4 core was modified to be backward-compatible with 32-bit PowerPC processors, and a vector unit (similar to the AltiVec extensions in Motorola's 74xx series) was added.

IBM's RS64 processors are a family of chips implementing the "Amazon" variant of the PowerPC architecture. These processors are used in the RS/6000 and IBM AS/400 computer families; the Amazon architecture includes proprietary extensions used by AS/400.[12] The POWER4 and later POWER processors implement the Amazon architecture and replaced the RS64 chips in the RS/6000 and AS/400 families.

IBM developed a separate product line called the "4xx" line focused on the embedded market. These designs included the 401, 403, 405, 440, and 460. In 2004, IBM sold their 4xx product line to Applied Micro Circuits Corporation (AMCC). AMCC continues to develop new high performance products, partly based on IBM's technology, along with technology that was developed within AMCC. These products focus on a variety of applications including networking, wireless, storage, printing/imaging and industrial automation.

Numerically, the PowerPC is mostly found in controllers in cars. For the automotive market, Freescale Semiconductor initially offered many variations called the MPC5xx family such as the MPC555, built on a variation of the 601 core called the 8xx and designed in Israel by MSIL (Motorola Silicon Israel Limited). The 601 core is single issue, meaning it can only issue one instruction in a clock cycle. To this they add various bits of custom hardware, to allow for I/O on the one chip. In 2004, the next-generation four-digit 55xx devices were launched for the automotive market. These use the newer e200 series of PowerPC cores.

Networking is another area where embedded PowerPC processors are found in large numbers. MSIL took the QUICC engine from the MC68302 and made the PowerQUICC MPC860. This was a very famous processor used in many Cisco edge routers in the late 1990s. Variants of the PowerQUICC include the MPC850, and the MPC823/MPC823e. All variants include a separate RISC microengine called the CPM that offloads communications processing tasks from the central processor and has functions for DMA. The follow-on chip from this family, the MPC8260, has a 603e-based core and a different CPM.

Honda also uses PowerPC processors for ASIMO.[13]

In 2003, BAE Systems Platform Solutions delivered the Vehicle-Management Computer for the F-35 fighter jet. This platform consists of dual PowerPCs made by Freescale in a triple redundant setup.[14]

Operating systems

Operating systems that work on the PowerPC architecture are generally divided into those that are oriented toward the general-purpose PowerPC systems, and those oriented toward the embedded PowerPC systems.

Operating systems with native support

Embedded

Licensees

Companies that have licensed the 64-bit POWER or 32-bit PowerPC from IBM include:

32-bit PowerPC

64-bit PowerPC

Game consoles

PowerPC processors were used in a number of now-discontinued video game consoles:

Desktop computers

The Power architecture is currently used in the following desktop computers:

  • Sam440ep, Sam440epFlex, based on an AMCC 440ep SoC, built by ACube Systems
  • Sam460ex, based on an AMCC 460ex SoC, built by ACube Systems
  • Nemo motherboard based around PA6T-1682M found in the AmigaOne X1000 from A-EON Technology
  • Cyrus motherboard based around Freescale Qoriq P5020 found in the AmigaOne X5000 from A-EON Technology
  • Tabor motherboard based around Freescale QorIQ P1022 found in the forthcoming AmigaOne A1222 from A-EON Technology
  • Talos II and Blackbird mainboards/workstations, based around the IBM Power9 Sforza architecture, built by Raptor Computing Systems

Embedded applications

The Power architecture is currently used in the following embedded applications:

See also

References

  1. ↑ 1.0 1.1 "PowerPC Architecture Book, Version 2.02". 16 November 2005. https://www.ibm.com/developerworks/systems/library/es-archguide-v2.html. 
  2. ↑ 2.0 2.1 2.2 2.3 Carlton, Jim (1999). Apple: The Inside Story of Intrigue, Egomania and Business Blunders. ISBN 978-0099270737. OCLC 925000937. 
  3. ↑ "Tech Files Columns, 1987–1990". http://www.joelwest.org/Press/TechFiles.html#01.03.89. 
  4. ↑ A. R. Kennedy; M. Alexander; E. Fiene; J. Lyon; B. Kuttanna; R. Patel; M. Pham; M. Putrino et al. (23 February 1997). "A G3 PowerPC superscalar low-power microprocessor". Proceedings IEEE COMPCON 97. Digest of Papers (IEEE): 315–324. doi:10.1109/CMPCON.1997.584742. https://ieeexplore.ieee.org/document/584742. Retrieved September 1, 2021. 
  5. ↑ Gwennap, Linley (16 November 1998). "G4 Is First PowerPC with AltiVec - Due Mid-1999, Motorola's Next Chip Aims at Macintosh, Networking". Microprocessor Report. http://www.eecg.toronto.edu/~moshovos/ACA07/lecturenotes/ppcg4%2520(mpr).pdf. 
  6. ↑ Seale, Susan (2001). "PowerPC G4 Architecture White Paper". https://www.nxp.com/docs/en/white-paper/G4WP.pdf. 
  7. ↑ "Fact Sheet - Motorola PowerPC Processor". https://www.nxp.com/docs/en/fact-sheet/PPCCPUINTFACT.pdf. 
  8. ↑ Necasek, Michal (16 November 2012). "OS/2 for PowerPC Tidbits". http://www.os2museum.com/wp/os2-for-powerpc-tidbits/. 
  9. ↑ Linley Gwennap (February 27, 1997). "Arthur Revitalizes PowerPC Line". Microprocessor Report 11 (2). https://pdfs.semanticscholar.org/9492/040bfd1226a08b25c92539fe4d724d01a5dc.pdf. "The 603’s tiny 8K caches were notoriously poor for Mac OS software, particularly for 68K emulation; even the 603e’s caches cause a significant performance hit at higher clock speeds. Given Arthur’s design target of 250 MHz and up, doubling the caches again made sense.". 
  10. ↑ Jansen, Daniel (2014). "CPUs: PowerPC 603 and 603e". Low End Mac. http://lowendmac.com/2014/cpus-powerpc-603-and-603e/. 
  11. ↑ "Microsoft killed the PowerPC 615". October 1, 1998. https://www.theregister.co.uk/1998/10/01/microsoft_killed_the_powerpc/. 
  12. ↑ Adam T. Stallman; Frank G. Soltis (July 1, 1995). "Inside the PowerPC AS". System iNEWS Magazine. http://iprodeveloper.com/systems-management/inside-powerpc. 
  13. ↑ Hara, Yoshiko (28 November 2000). "Latest robots fill helper, entertainer roles". EETimes.com. https://www.eetimes.com/latest-robots-fill-helper-entertainer-roles/. 
  14. ↑ "First Lockheed Martin F-35 Joint Strike Fighter Vehicle-Management Computer Delivered" (Press release). Lockheed Martin. May 16, 2003. Archived from the original on January 15, 2018. Retrieved January 14, 2018.
  15. ↑ "PowerPC - Unsupported Builds". https://download.haiku-os.org/nightly-images/ppc/. 
  16. ↑ "FreeBSD/ppc Project". Freebsd.org. http://www.freebsd.org/platforms/ppc.html. 
  17. ↑ "NetBSD/ofppc". Netbsd.org. http://www.netbsd.org/Ports/ofppc/. 
  18. ↑ "NetBSD/macppc". Netbsd.org. http://www.netbsd.org/Ports/macppc/. 
  19. ↑ "NetBSD/evbppc". Netbsd.org. http://www.netbsd.org/Ports/evbppc/. 
  20. ↑ "NetBSD/prep". Netbsd.org. http://wiki.netbsd.org/ports/prep/. 
  21. ↑ "NetBSD/mvmeppc". Netbsd.org. February 27, 2002. http://www.netbsd.org/Ports/mvmeppc/. 
  22. ↑ "NetBSD/bebox". Netbsd.org. http://www.netbsd.org/Ports/bebox/. 
  23. ↑ "NetBSD/amigappc". Netbsd.org. http://www.netbsd.org/Ports/amigappc/. 
  24. ↑ "OpenBSD/macppc". Openbsd.org. http://www.openbsd.org/macppc.html. 
  25. ↑ "CRUX PPC GNU/Linux Project". Cruxppc.org. http://www.cruxppc.org/. 
  26. ↑ "PowerPC Port". Debian. http://www.debian.org/ports/powerpc/. 
  27. ↑ "Chapter 3. Installation System". https://www.debian.org/releases/stable/amd64/release-notes/ch-installing.en.html#inst-changes. 
  28. ↑ "Debian PPC64 Port". Debian. http://wiki.debian.org/PPC64. 
  29. ↑ "Installable Live CD". Fedora Project. http://fedoraproject.org/get-fedora. 
  30. ↑ "Project:PowerPC". Gentoo Wiki. https://wiki.gentoo.org/wiki/Project:PowerPC. 
  31. ↑ "MintPPC". http://www.mintppc.org. 
  32. ↑ "Chapter 1. Architectures". https://access.redhat.com/documentation/en-US/Red_Hat_Enterprise_Linux/7/html/7.1_Release_Notes/chap-Red_Hat_Enterprise_Linux-7.1_Release_Notes-Architectures.html. 
  33. ↑ "PowerPCFAQ - Ubuntu Wiki". Wiki.ubuntu.com. https://wiki.ubuntu.com/PowerPCFAQ#head-8d764a92cbe82911913d972b8189698f9f04e6f3. 
  34. ↑ "Void Linux for PowerPC/Power ISA (unofficial)". https://voidlinux-ppc.org/. 
  35. ↑ "Embedded Solaris on PowerPC". Research.sun.com. June 14, 2006. http://labs.oracle.com/spotlight/2006/2006-06-14-SolarisPPC.html. 
  36. ↑ "Solaris PowerPC Port at OpenSolaris.org". Opensolaris.org. October 2, 2006. http://hub.opensolaris.org/bin/view/Project+ppc-dev/WebHome. 
  37. ↑ "Windows NT 3.5 for PowerPC". November 9, 1994. https://archive.org/details/NT3.5PPC. 
  38. ↑ "ReactOS ports - ReactOS Wiki". https://www.reactos.org/wiki/ReactOS_ports. 
  39. ↑ "DO-178C Certifiable Avionics RTOS with ARINC 653 & FACE Support". https://www.ddci.com/products_deos_do_178c_arinc_653/. 
  40. ↑ "Supported CPUs". http://www.sciopta.com/cpu/cpu.html. 
  41. ↑ "PowerPC 750FX Evaluation Kit Quick Setup for Windows". http://www.csit-sun.pub.ro/~cpop/Documentatie_SMP/IBM_PowerPC/750fxQuickStart.pdf. 
  42. ↑ 42.0 42.1 42.2 "POWER To The People". IBM. March 30, 2004. http://www.ibm.com/developerworks/power/library/pa-powerppl/. 

Further reading

External links




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