Engineering:5 nm process

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Short description: Semiconductor manufacturing processes at the 5 nm FinFET technology node

In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the 5 nm process as the MOSFET technology node following the 7 nm node. In 2020, Samsung and TSMC entered volume production of 5 nm chips, manufactured for companies including Apple, Marvell, Huawei and Qualcomm.[1][2]

The term "5 nm" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors being 5 nanometers in size. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a "5 nm node is expected to have a contacted gate pitch of 51 nanometers and a tightest metal pitch of 30 nanometers".[3] However, in real world commercial practice, "5 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption compared to the previous 7 nm process.[4][5]

History

Background

Quantum tunnelling effects through the gate oxide layer on 7 nm and 5 nm transistors became increasingly difficult to manage using existing semiconductor processes.[6] Single-transistor devices below 7 nm were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6-nanometre silicon-on-insulator (SOI) MOSFET.[7][8]

In 2003, a Japanese research team at NEC, led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first 5 nm MOSFET.[9][10]

In 2015, IMEC and Cadence had fabricated 5 nm test chips. The fabricated test chips are not fully functional devices but rather are to evaluate patterning of interconnect layers.[11][12]

In 2015, Intel described a lateral nanowire (or gate-all-around) FET concept for the 5 nm node.[13]

In 2017, IBM revealed that it had created 5 nm silicon chips,[14] using silicon nanosheets in a gate-all-around configuration (GAAFET), a break from the usual FinFET design. The GAAFET transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the same gate, just like FinFETs usually have several physical fins side by side that are electrically a single unit and are covered in their entirety by the same gate. IBM's chip measured 50 mm2 and had 600 million transistors per mm2, for a total of 30 billion transistors (1667 nm2 per transistor or 41 nm transistor spacing).[15][16]

Commercialization

In April 2019, Samsung Electronics announced they had been offering their 5 nm process (5LPE) tools to their customers since 2018 Q4.[17] In April 2019, TSMC announced that their 5 nm process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers. The N5 process can use EUVL on up to 14 layers, compared to only 5 or 4 layers in N6 and N7++.[18] For the expected 28 nm minimum metal pitch, SALELE is the proposed best patterning method.[19]

For their 5 nm process, Samsung started process defect mitigation by automated check and fix, due to occurrence of stochastic (random) defects in the metal and via layers.[20]

In October 2019, TSMC reportedly started sampling 5 nm A14 processors for Apple.[21]

In December 2019, TSMC announced an average yield of approximately 80%, with a peak yield per wafer of over 90% for their 5 nm test chips with a die size of 17.92 mm2.[22] In mid 2020 TSMC claimed its (N5) 5 nm process offered 1.8x the density of its 7 nm N7 process, with 15% speed improvement or 30% lower power consumption; an improved sub-version (N5P or N4) was claimed to improve on N5 with +5% speed or -10% power.[23]

On 13 October 2020, Apple announced a new iPhone 12 lineup using the A14. Together with the Huawei Mate 40 lineup using the HiSilicon Kirin 9000, the A14 and Kirin 9000 were the first devices to be commercialized on TSMC's 5 nm node. Later, on 10 November 2020, Apple also revealed three new Mac models using the Apple M1, another 5 nm chip. According to Semianalysis, the A14 processor has a transistor density of 134 million transistors per mm2.[24]

In October 2021, TSMC introduced a new member of its 5 nm process family: N4P. Compared to N5, the node offers 11% higher performance (6% higher vs N4), 22% higher power efficiency, 6% higher transistor density and lower mask count. TSMC expects first tapeouts by the second half of 2022.[25][26]

In December 2021, TSMC announced a new member of its 5 nm process family designed for HPC applications: N4X. The process features optimized transistor design and structures, reduced resistance and capacitance of targeted metal layers and high-density MiM capacitors. The process will offer up to 15% higher performance vs N5 (or up to 4% vs N4P) at 1.2 V and supply voltage in excess of 1.2 V. TSMC expects N4X to enter risk production by the first half of 2023.[27][28][29]

In June 2022, Intel presented some details about the Intel 4 process (known as 7 nm before renaming in 2021): the company's first process to use EUV, 2x higher transistor density compared to Intel 7 (known as 10 nm ESF (Enhanced Super Fin) before the renaming), use of cobalt-clad copper for the finest five layers of interconnect, 21.5% higher performance at iso power or 40% lower power at iso frequency at 0.65 V compared to Intel 7 etc. Intel's first product to be fabbed on Intel 4 is Meteor Lake, powered on in Q2 2022 and scheduled for shipping in 2023.[30] Intel 4 has contacted gate pitch of 50 nm, both fin and minimum metal pitch of 30 nm, and library height of 240 nm. Metal-insulator-metal capacitance was increased to 376 fF/μm², roughly 2x compared to Intel 7.[31] The process is optimized for HPC applications and supports voltage from <0.65 V to >1.3 V. WikiChip's transistor density estimate for Intel 4 is 123.4 Mtr./mm², 2.04x from 60.5 Mtr./mm² for Intel 7. However, high-density SRAM cell has scaled only by 0.77x (from 0.0312 to 0.024 μm²) and high-performance cell by 0.68x (from 0.0441 to 0.03 μm²) compared to Intel 7.[32]

On 27 September 2022, AMD officially launched their Ryzen 7000 series of central processing units, based on the TSMC 5 nm process and Zen 4 microarchitecture.[33] Zen 4 marks the first utilization of the 5 nm process for x86-based desktop processors. AMD also launched the Radeon 7000 series of graphics processing unit based on RDNA 3 which also uses TSMC 5 nm process.[34]

5 nm process nodes

5 nm
IRDS roadmap 2017[35] Samsung[36][37][38][39][40] TSMC[36]
Process name 7 nm 5 nm 5LPE 5LPP N5 N5P 4N[41]
Transistor density (MTr/mm2) Unknown Unknown 126.9[40] Unknown 138.2[42][43] Unknown
SRAM bit-cell size (μm2) 0.027[44] 0.020[44] 0.0262[45] 0.021[45] Unknown
Transistor gate pitch (nm) 48 42 57 51 Unknown
Interconnect pitch (nm) 28 24 36 Unknown 28[46] Unknown
Release status 2019 2021 2018 risk production[17]
2020 production 		2022 production 2019 risk production[18]
2020 production 		2020 risk production
2021 production 		2022 production

4 nm process nodes

Samsung[36][38][39][40][47] TSMC Intel[48][30]
Process name 4LPE 4LPP 4LPP+ 4HPC 4LPA N4 N4P N4X[27][28][29] 4
Transistor density (MTr/mm2) 137[40] Unknown Unknown Unknown 143.7[49] Unknown 123.4[32]
SRAM bit-cell size (μm2) 0.0262[45] Unknown Unknown Unknown Unknown Unknown Unknown 0.024[45]
Transistor gate pitch (nm) 57 Unknown Unknown Unknown 51 Unknown 50
Interconnect pitch (nm) 32 Unknown Unknown Unknown 28 Unknown 30
Release status 2020 risk production
2021 production 		2022 production 2023 production 2024 production 2025 production 2021 risk production
2022 production 		2022 risk production
2022 production 		Risk production by H1 2023
2024 production 		2022 risk production[50]
2023 production[51]

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch).[52][53]

Beyond 4 nm

3 nm (3-nanometer) is the usual term for the next node after 5 nm. (As of 2023), TSMC has started producing chips for select customers, while Samsung and Intel have plans for 2024.[48][54][55][56]

3.5 nm has also been given as a name for the first node beyond 5 nm.[57]

References

  1. ↑ Cutress, Dr Ian. "'Better Yield on 5nm than 7nm': TSMC Update on Defect Rates for N5". https://www.anandtech.com/show/16028/better-yield-on-5nm-than-7nm-tsmc-update-on-defect-rates-for-n5. 
  2. ↑ "Marvell and TSMC Collaborate to Deliver Data Infrastructure Portfolio on 5nm Technology". https://www.hpcwire.com/off-the-wire/marvell-and-tsmc-collaborate-to-deliver-data-infrastructure-portfolio-on-5nm-technology/. 
  3. ↑ International Roadmap for Devices and Systems: 2021 Update: More Moore, IEEE, 2021, p. 7, https://irds.ieee.org/editions/2021/more-moore, retrieved 7 August 2022 
  4. ↑ "TSMC's 7nm, 5nm, and 3nm "are just numbers… it doesn't matter what the number is"". 10 September 2019. https://www.pcgamesn.com/amd/tsmc-7nm-5nm-and-3nm-are-just-numbers. 
  5. ↑ Samuel K. Moore (21 July 2020). "A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric". IEEE Spectrum (IEEE). https://spectrum.ieee.org/semiconductors/devices/a-better-way-to-measure-progress-in-semiconductors. Retrieved 20 April 2021. 
  6. ↑ "Quantum Effects At 7/5nm And Beyond". Semiconductor Engineering. https://semiengineering.com/quantum-effects-at-7-5nm/. 
  7. ↑ "IBM claims world's smallest silicon transistor - TheINQUIRER". 9 December 2002. http://www.theinquirer.net/inquirer/news/1034321/ibm-claims-worlds-smallest-silicon-transistor. 
  8. ↑ Doris, Bruce B.; Dokumaci, Omer H.; Ieong, Meikei K.; Mocuta, Anda; Zhang, Ying; Kanarsky, Thomas S.; Roy, R. A. (December 2002). "Extreme scaling with ultra-thin Si channel MOSFETs". Digest. International Electron Devices Meeting. pp. 267–270. doi:10.1109/IEDM.2002.1175829. ISBN 0-7803-7462-2. 
  9. ↑ "NEC test-produces world's smallest transistor". http://www.thefreelibrary.com/NEC+test-produces+world%27s+smallest+transistor.-a0111295563. 
  10. ↑ Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K. et al. (December 2003). "Sub-10-nm planar-bulk-CMOS devices using lateral junction control". IEEE International Electron Devices Meeting 2003. pp. 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446. ISBN 0-7803-7872-5. 
  11. ↑ "IMEC and Cadence Disclose 5nm Test Chip". 4 July 2023. https://semiwiki.com/eda/cadence/5080-imec-and-cadence-disclose-5nm-test-chip/. 
  12. ↑ "The Roadmap to 5nm: Convergence of Many Solutions Needed". http://www.semi.org/en/node/55926. 
  13. ↑ Mark LaPedus (20 January 2016). "5nm Fab Challenges". http://semiengineering.com/5nm-fab-challenges/. "Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS)." 
  14. ↑ Sebastian, Anthony (5 June 2017). "IBM unveils world's first 5nm chip". https://arstechnica.com/gadgets/2017/06/ibm-5nm-chip/. 
  15. ↑ Huiming, Bu (5 June 2017). "5 nanometer transistors inching their way into chips". https://www.ibm.com/blogs/think/2017/06/5-nanometer-transistors/. 
  16. ↑ "IBM Figures Out How to Make 5nm Chips". 5 June 2017. http://uk.pcmag.com/news/89652/ibm-figures-out-how-to-make-5nm-chips. 
  17. ↑ 17.0 17.1 Shilov, Anton. "Samsung Completes Development of 5nm EUV Process Technology". https://www.anandtech.com/show/14231/samsung-completes-development-of-5-nm-euv-process-technology. 
  18. ↑ 18.0 18.1 "TSMC and OIP Ecosystem Partners Deliver Industry's First Complete Design Infrastructure for 5nm Process Technology" (Press release). TSMC. 3 April 2019.
  19. ↑ "SALELE Double Patterning for 7nm and 5nm Nodes". https://www.linkedin.com/pulse/salele-double-patterning-7nm-5nm-nodes-frederick-chen. 
  20. ↑ Jaehwan Kim; Jin Kim; Byungchul Shin; Sangah Lee; Jae-Hyun Kang; Joong-Won Jeon; Piyush Pathak; Jac Condella et al. (23 March 2020). "Process related yield risk mitigation with in-design pattern replacement for system ICs manufactured at advanced technology nodes". Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280I. San Jose, California, United States. doi:10.1117/12.2551970. 
  21. ↑ Solca, Bogdan (22 October 2019). "TSMC already sampling Apple's 5 nm A14 Bionic SoCs for 2020 iPhones". https://www.notebookcheck.net/TSMC-already-sampling-Apple-s-5-nm-A14-Bionic-SoCs-for-2020-iPhones.440058.0.html. 
  22. ↑ Cutress, Dr Ian. "Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020". https://www.anandtech.com/show/15219/early-tsmc-5nm-test-chip-yields-80-hvm-coming-in-h1-2020. 
  23. ↑ Hruska, Joel (25 August 2020). "TSMC Plots an Aggressive Course for 3nm Lithography and Beyond". https://www.extremetech.com/computing/314204-tsmc-plots-an-aggressive-course-for-3nm-lithography-and-beyond. 
  24. ↑ Patel, Dylan (27 October 2020). "Apple's A14 Packs 134 Million Transistors/mm², but Falls Short of TSMC's Density Claims". https://semianalysis.com/apples-a14-packs-134-million-transistors-mm2-but-falls-far-short-of-tsmcs-density-claims/. 
  25. ↑ "TSMC Expands Advanced Technology Leadership with N4P Process". TSMC (Press release). 26 October 2021.
  26. ↑ "TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node". 26 October 2021. https://fuse.wikichip.org/news/6439/tsmc-extends-its-5nm-family-with-a-new-enhanced-performance-n4p-node/. 
  27. ↑ 27.0 27.1 "TSMC Introduces N4X Process" (Press release). TSMC. 16 December 2021.
  28. ↑ 28.0 28.1 "The Future Is Now (blog post)". 16 December 2021. https://www.tsmc.com/english/news-events/blog-article-20211216. 
  29. ↑ 29.0 29.1 "TSMC Unveils N4X Node". 17 December 2021. https://www.anandtech.com/print/17123/tsmc-unveils-n4x-node-high-voltages-for-high-clocks. 
  30. ↑ 30.0 30.1 Smith, Ryan. "Intel 4 Process Node In Detail: 2x Density Scaling, 20% Improved Performance". https://www.anandtech.com/show/17448/intel-4-process-node-in-detail-2x-density-scaling-20-improved-performance. 
  31. ↑ Jones, Scotten (13 June 2022). "Intel 4 Deep Dive". https://semiwiki.com/semiconductor-manufacturers/intel/314047-intel-4-presented-at-vlsi/. 
  32. ↑ 32.0 32.1 Schor, David (19 June 2022). "A Look At Intel 4 Process Technology". https://fuse.wikichip.org/news/6720/a-look-at-intel-4-process-technology/. 
  33. ↑ "AMD Launches Ryzen 7000 Series Desktop Processors with "Zen 4" Architecture: the Fastest Core in Gaming" (Press release). 29 August 2022. Retrieved 31 March 2023.
  34. ↑ Wickens, Katie (30 August 2022). "AMD's Lisa Su confirms chiplet-based RDNA 3 GPU architecture". https://www.pcgamer.com/amds-lisa-su-confirms-chiplet-based-rdna-3-gpu-architecture/. 
  35. ↑ "IRDS international roadmap for devices and systems 2017 edition". https://irds.ieee.org/images/files/pdf/2017/2017IRDS_MM.pdf. 
  36. ↑ 36.0 36.1 36.2 Jones, Scotten (29 April 2020), Can TSMC Maintain Their Process Technology Lead, https://semiwiki.com/semiconductor-manufacturers/intel/285192-can-tsmc-maintain-their-process-technology-lead/, retrieved 11 April 2022 
  37. ↑ "Samsung Foundry Update 2019". 6 August 2019. https://semiwiki.com/semiconductor-manufacturers/samsung-foundry/259664-samsung-foundry-update-2019/. 
  38. ↑ 38.0 38.1 "Samsung 5 nm and 4 nm Update". 19 October 2019. https://fuse.wikichip.org/news/2823/samsung-5-nm-and-4-nm-update/. 
  39. ↑ 39.0 39.1 "5 nm lithography process". https://en.wikichip.org/wiki/5_nm_lithography_process. 
  40. ↑ 40.0 40.1 40.2 40.3 "Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements". 5 July 2022. https://fuse.wikichip.org/news/6932/samsung-3nm-gaafet-enters-risk-production-discusses-next-gen-improvements/. 
  41. ↑ "NVIDIA Delivers Quantum Leap in Performance, Introduces New Era of Neural Rendering With GeForce RTX 40 Series". http://nvidianews.nvidia.com/news/nvidia-delivers-quantum-leap-in-performance-introduces-new-era-of-neural-rendering-with-geforce-rtx-40-series. 
  42. ↑ "The TRUTH of TSMC 5nm". https://www.angstronomics.com/p/the-truth-of-tsmc-5nm. 
  43. ↑ "N3E Replaces N3; Comes in Many Flavors". 4 September 2022. https://fuse.wikichip.org/news/7048/n3e-replaces-n3-comes-in-many-flavors/. 
  44. ↑ 44.0 44.1 INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2017 EDITION - MORE MOORE, ITRS, 2017, Section 4.5 Table MM-10 (p.12) entries : "SRAM bitcell area (um2)" ; "SRAM 111 bit cell area density - Mbits/mm2", https://irds.ieee.org/images/files/pdf/2017/2017IRDS_MM.pdf, retrieved 24 October 2018 
  45. ↑ 45.0 45.1 45.2 45.3 "Did We Just Witness The Death Of SRAM?". 4 December 2022. https://fuse.wikichip.org/news/7343/iedm-2022-did-we-just-witness-the-death-of-sram/. 
  46. ↑ J.C. Liu. "A Reliability Enhanced 5nm CMOS Technology Featuring 5th Generation FinFET with Fully-Developed EUV and High Mobility Channel for Mobile SoC and High Performance Computing Application". 2020 IEEE International Electron Devices Meeting (IEDM). doi:10.1109/IEDM13553.2020.9372009. 
  47. ↑ "Samsung Foundry Vows to Surpass TSMC within Five Years". https://www.anandtech.com/show/18854/-samsung-foundry-vows-to-surpass-tsmc-within-five-years. 
  48. ↑ 48.0 48.1 Cutress, Dr Ian. "Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!". https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros. 
  49. ↑ "TSMC N3, and Challenges Ahead". 27 May 2023. https://fuse.wikichip.org/news/7375/tsmc-n3-and-challenges-ahead/. 
  50. ↑ Gartenberg, Chaim (29 July 2021). "The summer Intel fell behind". The Verge. https://www.theverge.com/22597713/intel-7nm-delay-summer-2020-apple-arm-switch-roadmap-gelsinger-ceo. 
  51. ↑ https://www.anandtech.com/show/20046/intel-unveils-meteor-lake-architecture-intel-4-heralds-the-disaggregated-future-of-mobile-cpus/2
  52. ↑ "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report". https://www.semiconductors.org/clientuploads/Research_Technology/ITRS/2015/0_2015%20ITRS%202.0%20Executive%20Report%20(1).pdf. 
  53. ↑ "5 nm lithography process". https://en.wikichip.org/wiki/5_nm_lithography_process. 
  54. ↑ "Samsung 3 nm GAAFET Node Delayed to 2024". 30 June 2021. https://www.techpowerup.com/283983/samsung-3-nm-gaafet-node-delayed-to-2024. 
  55. ↑ Shilov, Anton. "Samsung: Deployment of 3nm GAE Node on Track for 2022". https://www.anandtech.com/show/16815/samsung-deployment-of-3nm-gae-on-track-for-2022. 
  56. ↑ Shilov, Anton. "TSMC Update: 2nm in Development, 3nm and 4nm on Track for 2022". https://www.anandtech.com/show/16639/tsmc-update-2nm-in-development-3nm-4nm-on-track-for-2022. 
  57. ↑ "15 Views from a Silicon Summit: Macro to nano perspectives of chip horizon". 16 January 2017. https://www.eetimes.com/document.asp?doc_id=1331185. 

External links


Preceded by
7 nm (FinFET) 		MOSFET semiconductor device fabrication process Succeeded by
3 nm (FinFET/GAAFET)



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