Communication-avoiding algorithm

Communication-avoiding algorithms minimize movement of data within a memory hierarchy for improving its running-time and energy consumption. These minimize the total of two costs (in terms of time and energy): arithmetic and communication. Communication, in this context refers to moving data, either between levels of memory or between multiple processors over a network. It is much more expensive than arithmetic.

Formal theory

Two-level memory model

A common computational model in analyzing communication-avoiding algorithms is the two-level memory model:

• There is one processor and two levels of memory.
• Level 1 memory is infinitely large. Level 0 memory ("cache") has size [math]\displaystyle{ M }[/math].
• In the beginning, input resides in level 1. In the end, the output resides in level 1.
• Processor can only operate on data in cache.
• The goal is to minimize data transfers between the two levels of memory.

Matrix multiplication

Corollary 6.2:

Theorem — Given matrices [math]\displaystyle{ A, B, C }[/math] of sizes [math]\displaystyle{ n\times m, m \times k, n\times k }[/math], then [math]\displaystyle{ AB + C }[/math] has communication complexity [math]\displaystyle{ \Omega(\max(mkn/M^{1/2}, mk+kn+mk)) }[/math].

This lower bound is achievable by tiling matrix multiplication.

More general results for other numerical linear algebra operations can be found in. The following proof is from.

Proof

We can draw the computation graph of [math]\displaystyle{ D = AB + C }[/math] as a cube of lattice points, each point is of form [math]\displaystyle{ (i,j,k) }[/math]. Since [math]\displaystyle{ D[i,k] = \sum_j A[i,j]B[j,k] + C[i,k] }[/math], computing [math]\displaystyle{ AB+C }[/math] requires the processor to have access to each point within the cube at least once. So the problem becomes covering the [math]\displaystyle{ mnk }[/math] lattice points with a minimal amount of communication.

If [math]\displaystyle{ M }[/math] is large, then we can simply load all [math]\displaystyle{ mn+nk+mk }[/math] entries then write [math]\displaystyle{ nk }[/math] entries. This is uninteresting.

If [math]\displaystyle{ M }[/math] is small, then we can divide the minimal-communication algorithm into separate segments. During each segment, it performs exactly [math]\displaystyle{ M }[/math] reads to cache, and any number of writes from cache.

During each segment, the processor has access to at most [math]\displaystyle{ 2M }[/math] different points from [math]\displaystyle{ A, B, C }[/math].

Let [math]\displaystyle{ E }[/math] be the set of lattice points covered during this segment. Then by the Loomis–Whitney inequality,

[math]\displaystyle{ |E| \leq \sqrt{|\pi_1(E)||\pi_2(E)||\pi_3(E)|} }[/math] with constraint [math]\displaystyle{ \sum_i |\pi_i(E)| \leq 2M }[/math].

By the inequality of arithmetic and geometric means, we have [math]\displaystyle{ |E| \leq \left(\frac 23 M\right)^{3/2} }[/math], with extremum reached when [math]\displaystyle{ \pi_i(E) = \frac 23 M }[/math].

Thus the arithmetic intensity is bounded above by [math]\displaystyle{ CM^{1/2} }[/math] where [math]\displaystyle{ C = (2/3)^{3/2} }[/math], and so the communication is bounded below by [math]\displaystyle{ \frac{nmk}{CM^{1/2}} }[/math].

Direct computation verifies that the tiling matrix multiplication algorithm reaches the lower bound.

Motivation

Consider the following running-time model:

• Measure of computation = Time per FLOP = γ
• Measure of communication = No. of words of data moved = β

⇒ Total running time = γ·(no. of FLOPs) + β·(no. of words)

From the fact that β >> γ as measured in time and energy, communication cost dominates computation cost. Technological trends indicate that the relative cost of communication is increasing on a variety of platforms, from cloud computing to supercomputers to mobile devices. The report also predicts that gap between DRAM access time and FLOPs will increase 100× over coming decade to balance power usage between processors and DRAM.

FLOP rate (γ)	DRAM bandwidth (β)	Network bandwidth (β)
59% / year	23% / year	26% / year

Energy cost of data movement in 2010: On-chip vs Off-chip

Energy consumption increases by orders of magnitude as we go higher in the memory hierarchy.

United States president Barack Obama cited communication-avoiding algorithms in the FY 2012 Department of Energy budget request to Congress:

New Algorithm Improves Performance and Accuracy on Extreme-Scale Computing Systems. On modern computer architectures, communication between processors takes longer than the performance of a floating-point arithmetic operation by a given processor. ASCR researchers have developed a new method, derived from commonly used linear algebra methods, to minimize communications between processors and the memory hierarchy, by reformulating the communication patterns specified within the algorithm. This method has been implemented in the TRILINOS framework, a highly-regarded suite of software, which provides functionality for researchers around the world to solve large scale, complex multi-physics problems.

Objectives

Communication-avoiding algorithms are designed with the following objectives:

• Reorganize algorithms to reduce communication across all memory hierarchies.
• Attain the lower-bound on communication when possible.

The following simple example demonstrates how these are achieved.

Matrix multiplication example

Let A, B and C be square matrices of order n × n. The following naive algorithm implements C = C + A * B:

 for i = 1 to n
     for j = 1 to n
         for k = 1 to n
             C(i,j) = C(i,j) + A(i,k) * B(k,j)

Arithmetic cost (time-complexity): n²(2n − 1) for sufficiently large n or O(n³).

Rewriting this algorithm with communication cost labelled at each step

 for i = 1 to n
     {read row i of A into fast memory}               - n² reads
     for j = 1 to n
         {read C(i,j) into fast memory}               - n² reads
         {read column j of B into fast memory}        - n³ reads
         for k = 1 to n
             C(i,j) = C(i,j) + A(i,k) * B(k,j)
         {write C(i,j) back to slow memory}           - n² writes

Fast memory may be defined as the local processor memory (CPU cache) of size M and slow memory may be defined as the DRAM.

Communication cost (reads/writes): n³ + 3n² or O(n³)

Since total running time = γ·O(n³) + β·O(n³) and β >> γ the communication cost is dominant. The blocked (tiled) matrix multiplication algorithm reduces this dominant term:

Blocked (tiled) matrix multiplication

Consider A, B and C to be n/b-by-n/b matrices of b-by-b sub-blocks where b is called the block size; assume three b-by-b blocks fit in fast memory.

 for i = 1 to n/b
     for j = 1 to n/b
         {read block C(i,j) into fast memory}           - b² × (n/b)² = n² reads
         for k = 1 to n/b
             {read block A(i,k) into fast memory}       - b² × (n/b)³ = n³/b reads 
             {read block B(k,j) into fast memory}       - b² × (n/b)³ = n³/b reads
             C(i,j) = C(i,j) + A(i,k) * B(k,j)          - {do a matrix multiply on blocks}
         {write block C(i,j) back to slow memory}       - b² × (n/b)² = n² writes

Communication cost: 2n³/b + 2n² reads/writes << 2n³ arithmetic cost

Making b as large possible:

3b² ≤ M

we achieve the following communication lower bound:

3^1/2n³/M^1/2 + 2n² or Ω (no. of FLOPs / M^1/2)

Previous approaches for reducing communication

Most of the approaches investigated in the past to address this problem rely on scheduling or tuning techniques that aim at overlapping communication with computation. However, this approach can lead to an improvement of at most a factor of two. Ghosting is a different technique for reducing communication, in which a processor stores and computes redundantly data from neighboring processors for future computations. Cache-oblivious algorithms represent a different approach introduced in 1999 for fast Fourier transforms, and then extended to graph algorithms, dynamic programming, etc. They were also applied to several operations in linear algebra as dense LU and QR factorizations. The design of architecture specific algorithms is another approach that can be used for reducing the communication in parallel algorithms, and there are many examples in the literature of algorithms that are adapted to a given communication topology.

See also

• Data locality