Engineering:130 nm process
The 130 nm (0.13 μm) process refers to the level of MOSFET (CMOS) semiconductor process technology that was commercialized around the 2001–2002 timeframe, by leading semiconductor companies like Fujitsu,[1] IBM, Intel, Texas Instruments, and TSMC.
The origin of the 130 nm value is historical, as it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).
Some of the first CPUs manufactured with this process include Intel Tualatin family of Pentium III processors.
Background
Their first MOSFET demonstrated by Egyptian engineer Mohamed Atalla and Korean engineer Dawon Kahng in 1960 had a gate length of 20 μm and a gate oxide thickness of 100 nm.[2] In 1984, a MOSFET based on NMOS logic was fabricated with a 100 nm channel length by Toshio Kobayashi, Seiji Horiguchi and K. Kiuchi at Nippon Telegraph and Telephone (NTT) in Japan.[3]
In 1990, a 100 nm CMOS process was demonstrated by an IBM T.J. Watson Research Center team led by Iranian engineers Ghavam G. Shahidi and Bijan Davari and Taiwanese engineer Yuan Taur.[4] In 2001, 100 nm CMOS nodes were commercialized by Fujitsu[1] and IBM.
Processors using 130 nm manufacturing technology
- Fujitsu SPARC64 V – 2001[5]
- Gekko by IBM and Nintendo (GameCube console) – 2001
- Intel Pentium III Tualatin – 2001-06
- VIA C3 – 2001
- Motorola PowerPC 7447 and 7457 – 2002
- AMD Athlon MP Thoroughbred – 2002-08-27
- Vortex 86SX — 2007[6]
- Elbrus 2000 1891ВМ4Я (1891VM4YA) – 2008-04-27 [7]
- MCST-R500S 1891BM3 – 2008-07-27 [8]
References
- ↑ 1.0 1.1 65nm CMOS Process Technology
- ↑ Sze, Simon M. (2002). Semiconductor Devices: Physics and Technology (2nd ed.). Wiley. p. 4. ISBN 0-471-33372-7.
- ↑ Kobayashi, Toshio; Horiguchi, Seiji; Kiuchi, K. (December 1984). "Deep-submicron MOSFET characteristics with 5 nm gate oxide". 1984 International Electron Devices Meeting: 414–417. doi:10.1109/IEDM.1984.190738.
- ↑ Shahidi, Ghavam G.; Davari, Bijan; Taur, Yuan; Warnock, James D.; Wordeman, Matthew R.; McFarland, P. A.; Mader, S. R.; Rodriguez, M. D. (December 1990). "Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing". International Technical Digest on Electron Devices: 587–590. doi:10.1109/IEDM.1990.237130.
- ↑ Krewell, Kevin (21 October 2002). "Fujitsu's SPARC64 V Is Real Deal". Microprocessor Report.
- ↑ "CPU from DM&P". Dmp.com.tw. http://www.dmp.com.tw/.
- ↑ "Error: no
|title=specified when using {{Cite web}}" (in ru). Mcst.ru. http://www.mcst.ru/b_4-5.shtml. - ↑ "Микропроцессор МЦСТ R500S/МЦСТ" (in ru). Mcst.ru. http://www.mcst.ru/b_18-19.shtml.
| Preceded by 180 nm |
MOSFET manufacturing processes | Succeeded by 90 nm |
 |
