Biography:Trevor Mudge

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Short description: American university teacher
Trevor Mudge
OccupationComputer scientist, academic and researcher
AwardsACM/IEEE CS Eckert-Mauchly Award, ACM and IEEE Computer Society
Academic background
EducationB.Sc., Cybernetics, University of Reading
M.S., Computer Science, University of Illinois
Ph.D., Computer Science, University of Illinois
ThesisSEMANTRIX: A Semantically Guided Digital Electronic Machine (1973)
A Computer Hardware Design Language for Multiprocessor Systems (1977)
Academic work
InstitutionsUniversity of Michigan

Trevor Mudge is a computer scientist, academic and researcher. He is the Bredt Family Chair of Computer Science and Engineering, and Professor of Electrical Engineering and Computer Science at the University of Michigan.[1]

His research interests include computer systems design, low power computing, computer-aided design, parallel processing, and the impact of technology. Mudge has authored numerous publications. He also holds over forty United States Patents for his inventions in the field of Computer Science. In 2014 he received the ACM/IEEE CS Eckert-Mauchly Award—the computer architecture community’s most prestigious award—“for pioneering contributions to low-power computer architecture and its interaction with technology”. He has been inducted into the MICRO Hall of fame,[2] and International Symposium on Computer Architecture Hall of Fame.[3]

Mudge is a Life Fellow of the IEEE Computer Society, and a Fellow of the Association for Computing Machinery.[4]

Education

Mudge studied at the University of Reading and obtained a Bachelor's degree in Cybernetics, with a minor in Mathematics, in 1969. He then moved to the United States and enrolled in the University of Illinois, where he earned his Master's degree and Doctoral degree in Computer Science in 1973 and 1977, respectively.[1]

Career

Following his Bachelor's degree, Mudge joined the University of Illinois at Urbana-Champaign, and held an appointment as a research assistant in Digital Computer Laboratory in 1970, and in the Coordinated Science Laboratory in 1974. After graduation he joined the University of Michigan in 1977 as Assistant Professor of Electrical Engineering and Computer Science. He was promoted to Associate Professor in 1984, and to Professor of Electrical Engineering and Computer Science in 1990. In 2002 he became the Bredt Family Chair of Computer Science and Electrical Engineering at The University of Michigan.[5]

Research

Mudge has worked extensively on computer architecture, with specific emphasis on computer systems design, computer-aided design, parallel processing, low power computing, and the impact of technology. His research has been characterized by the construction of prototypes as proof of concept.

Mudge and his colleagues developed the concept of runahead.[6] He has shown the effectiveness of point-to-point crossbars for systems with less than a few hundred processors.[7]

Mudge conducted a design study into a fully programmable architecture, SODA, to support software defined radio.[8] An industrial prototype was constructed by the Arm Ltd.[9] He and colleagues developed the first optimal clocking timing algorithms for latch based digital systems: the SMO algorithm.[10][11]

Mudge was one of the first to propose that power be a primary microprocessor design constraint on a par with performance.[12][13] In this connection, he and his colleagues developed “drowsy” caches.[14]

In 2003, Mudge and his colleagues suggested a new approach to DVS, known as Razor, employed in dynamic detection and correction regarding circuit timing errors.[15]

Mudge and his colleagues explored the idea of operating chips at near-threshold voltages to further reduce power consumption.[16] They also built a proof-of-concept prototype 3-dimensional die stacking prototype, and a proof-of-concept prototype 64-core prototype, Centipede. He was an early advocate of 3-dimensional die stacking architecture to save energy.[17]

Awards and honors

  • 1995 - Fellow, Institute of Electrical and Electronics Engineers, “For contributions to the design and analysis of high-performance processors”
  • 1996 - Heaviside Premium. Awarded by the Institution of Electrical Engineer for the best paper of the year: “A comparison of two common pipeline structures” (with M. Golden)
  • 2003 - Bredt Family Chair of Engineering, the College of Engineering, University of Michigan[18]
  • 2007 - Microprocessor Report Analysts' Choice Award in the Innovation category, “RAZOR—Error-Tolerant Approach Supports Speculative Correctness”
  • 2012 - Most Influential Paper Award over the past 10 years from International Conference on Computer-Aided Design’s Ten-Year Retrospective for “Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads” (with S. Martin, K. Flautner, and D. Blaauw)
  • 2013 - Life Fellow, IEEE Computer Society
  • 2014 - Eckert-Mauchly Award, ACM and IEEE Computer Society, “For pioneering contributions to low-power computer architecture and its interaction with technology”
  • 2014 - Int. Conf. Supercomputing 35 most influential paper in the past 25 years for “Improving data cache performance by pre-executing instructions under a cache miss” (with J. Dundas)
  • 2017 - Distinguished Achievement Award, University of Illinois Computer Science Department[19]
  • 2017 - Fellow, Association for Computing Machinery, “For contributions to power aware computer architecture”
  • 2017 – Most Influential Paper Award over the past 15 years for “Drowsy Caches: Simple Techniques for Reducing Leakage Power”, a paper with the most impact over the past 15 years from the ISCA proceedings (with K. Flautner, N. Kim, S. Martin, and D. Blaauw)
  • 2018 - Most Impactful Paper—25 years Award, International Conference on High-Performance Computing

Bibliography

  • Dundas and T. Mudge. Improving data cache performance by pre-executing instructions under a cache miss. Proc. 1997 ACM Int. Conf. on Supercomputing, July 1997, pp. 68–75.
  • Ernst, D., Kim, N. S., Das, S., Pant, S., Rao, R., Pham, T., ...& Mudge, T. (2003, December). Razor: A low-power pipeline based on circuit-level timing speculation. In Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36. (pp. 7–18). IEEE.
  • Kim, N. S., Austin, T., Baauw, D., Mudge, T., Flautner, K., Hu, J. S., ...& Narayanan, V. (2003). Leakage current: Moore's law meets static power. computer, 36(12), 68-75.
  • Flautner, K., Kim, N. S., Martin, S., Blaauw, D., & Mudge, T. (2002). Drowsy caches: Simple techniques for reducing leakage power. ACM SIGARCH Computer architecture news, 30(2), 148-157.
  • Dreslinski, R. G., Wieckowski, M., Blaauw, D., Sylvester, D., & Mudge, T. (2010). Near-threshold computing: Reclaiming moore's law through energy efficient integrated circuits. Proceedings of the IEEE, 98(2), 253-266.

References

  1. ↑ 1.0 1.1 "Trevor Mudge –101010". https://tnm.engin.umich.edu/. 
  2. ↑ "MICRO Hall of Fame". https://www.sigmicro.org/micro-hall-of-fame/. 
  3. ↑ "An International Symposium on Computer Architecture (ISCA) Hall of Fame". http://pages.cs.wisc.edu/~arch/www/iscabibhall.html. 
  4. ↑ "Prof. Trevor Mudge named ACM Fellow for contributions to power aware computer architecture". https://cse.engin.umich.edu/stories/prof-trevor-mudge-named-acm-fellow-for-contributions-to-power-aware-computer-architecture. 
  5. ↑ "Trevor Mudge –101010". https://tnm.engin.umich.edu/. 
  6. ↑ Dundas, James; Mudge, Trevor (1997). "Improving data cache performance by pre-executing instructions under a cache miss". Proceedings of the 11th international conference on Supercomputing - ICS '97. pp. 68–75. doi:10.1145/263580.263597. ISBN 0897919025. https://dl.acm.org/doi/10.1145/263580.263597. 
  7. ↑ "Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration". https://web.eecs.umich.edu/~subh/publication/transmuter-pact20/transmuter-pact20.pdf. 
  8. ↑ Yuan Lin; Hyunseok Lee; Woh, M.; Harel, Y.; Mahlke, S.; Mudge, T.; Chakrabarti, C.; Flautner, K. (2006). "SODA: A Low-power Architecture For Software Radio". 33rd International Symposium on Computer Architecture (ISCA'06). pp. 89–101. doi:10.1109/ISCA.2006.37. ISBN 0-7695-2608-X. https://ieeexplore.ieee.org/document/1635943. 
  9. ↑ Woh, Mark; Lin, Yuan; Seo, Sangwon; Mahlke, Scott; Mudge, Trevor; Chakrabarti, Chaitali; Bruce, Richard; Kershaw, Danny et al. (2008). "From SODA to scotch: The evolution of a wireless baseband processor". 2008 41st IEEE/ACM International Symposium on Microarchitecture. pp. 152–163. doi:10.1109/MICRO.2008.4771787. ISBN 978-1-4244-2836-6. https://dl.acm.org/doi/10.1109/MICRO.2008.4771787. 
  10. ↑ "CheckTc and minTc: timing verification and optimal clocking of synchronous digital circuits". https://www.researchgate.net/publication/3504488. 
  11. ↑ "CLOCK DISTRIBUTION IN SYNCHRONOUS SYSTEMS". http://www2.ece.rochester.edu/users/friedman/papers/Wiley_99_CDN.pdf. 
  12. ↑ Nam Sung Kim; Austin, T.; Blaauw, D.; Mudge, T.; Flautner, K.; Jie s. Hu; Irwin, M.J.; Kandemir, M. et al. (2003). "Leakage Current: Moore's Law Meets Static Power". Computer 36 (12): 68–75. doi:10.1109/MC.2003.1250885. https://dl.acm.org/doi/10.1109/MC.2003.1250885. 
  13. ↑ Mudge, T. (2001). "Power: a first-class architectural design constraint". Computer 34 (4): 52–58. doi:10.1109/2.917539. https://ieeexplore.ieee.org/document/917539. 
  14. ↑ Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. 18 November 2002. pp. 219–230. ISBN 9780769518596. https://dl.acm.org/doi/10.5555/774861.774885. 
  15. ↑ Ernst, D.; Nam Sung Kim; Das, S.; Pant, S.; Rao, R.; Toan Pham; Ziesler, C.; Blaauw, D. et al. (2003). "Razor: a low-power pipeline based on circuit-level timing speculation". 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449). pp. 7–18. doi:10.1109/MICRO.2003.1253179. ISBN 0-7695-2043-X. https://ieeexplore.ieee.org/document/1253179. 
  16. ↑ Dreslinski, Ronald G.; Wieckowski, Michael; Blaauw, David; Sylvester, Dennis; Mudge, Trevor (2010). "Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits". Proceedings of the IEEE 98 (2): 253–266. doi:10.1109/JPROC.2009.2034764. https://ieeexplore.ieee.org/document/5395763. 
  17. ↑ Kgil, Taeho; d'Souza, Shaun; Saidi, Ali; Binkert, Nathan; Dreslinski, Ronald; Mudge, Trevor; Reinhardt, Steven; Flautner, Krisztian (20 October 2006). "PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor". ACM Sigops Operating Systems Review 40 (5): 117–128. doi:10.1145/1168917.1168873. https://dl.acm.org/doi/abs/10.1145/1168917.1168873. 
  18. ↑ "Professorships". https://cse.engin.umich.edu/people/honors-and-awards/faculty-honors-and-awards/professorships/. 
  19. ↑ "Alumni Awards Past Recipients". https://cs.illinois.edu/about/awards/alumni-awards/alumni-awards-past-recipients. 




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