MIPI I3C sensor interface standard

MIPI I3C

Type	Bus
Production history
Designer	MIPI Alliance Sensor Working Group
Designed	2016 (2016)
Manufacturer	multiple
Hot pluggable	true
Electrical
Signal	CMOS
Data
Data signal	Open-drain or Push/Pull
Width	2 wires [data + clock]
Bitrate	12.5 Mbit/s (SDR, standard), 25 Mbit/s (DDR), 33 Mbit/s (ternary), legacy I2C rates 400 Kbits/s (FM), 1 Mbit/s (FM+)
Protocol	Serial, half-duplex

The MIPI I3C Sensor Interface Specification (also known as SenseWire) is an emerging industry standard for multidrop serial data buses. I3C was developed as a collaborative effort between electronics and computer related companies under auspices of the Mobile Industry Processor Interface Alliance (MIPI Alliance.) I3C is an evolution of I2C, a de facto standard two-pin serial bus widely used for low-speed peripherals and sensors in computer systems. I3C adds a significant number of system interface features while retaining upward compatibility with existing I2C slave devices while native I3C devices support higher data rates (similar to SPI.) Like I2C, I3C uses two signal pins named SDA and SCL. One or more master devices can be connected to one or more slaves over the bus.

Google and Intel have backed I3C as a sensor interface standard for Internet of things (IoT) devices. With public release of the I3C specification, MIPI has begun a push for adoption in the mobile electronics and related industries.

History

Goals of the MIPI Sensor Working Group effort were first announced in November 2014 at the MEMS Executive Congress in Scottsdale AZ.

Electronic Design Automation tool vendors Cadence, Synopsys and NXP/Silvaco have released controller IP blocks and simulators designed to make implementing the MIPI I3C in new integrated circuit designs easier including FPGA based designs and ASICs

In December 2016, Lattice Semiconductor has integrated I3C support into its new FPGA known as an iCE40 Ultra Plus. making the bus available at relatively low cost for embedded systems designs.

In March 2017, Qualcomm has integrated I3C master support into its new mobile SOC known as an SDM845. making first on the market support for new protocol for mobile/automotive systems.

In December 2017, The I3C 1.0 specification was been released for public review. At about the same time, a Linux Kernel by patch introducing support for I3C was proposed by Boris Brezillon.

Goals

Prior to public release of the specification, a substantial amount of general information about it has been published in the form of slides from the 2016 MIPI DevCon. The goals for this interface were based on a survey of MIPI member organizations and MEMS Industry Group (MIG) members. The results of this survey have been made public.

Key I3C design enhancement (over I2C) include:

• Low-power and space effacement design intended for mobile devices (smartphones and IoT devices.)
• Two-pin interface that is a superset of the I2C standard. Legacy I2C slave devices can be connected the newer bus.
• In-band interrupts over the serial bus rather than requiring separate pins
• Standard Data Rate (SDR) throughput up to 10 Mbit/s using CMOS I/O levels (maximum bit rate 12.5Mbit/s),
• High Data Rate (HDR) modes permitting throughput comparable to SPI while requiring at a fraction of I2C Fast Mode power.
• A standardized set of common command codes
• Command queue support
• Error Detection and Recovery (parity and CRC)
• Dynamic address assignment (DAA) for I3C slaves, while still supporting static addresses for legacy devices
• Hot-join (some devices on the bus may be powered on/off during operation)
• Multi-master operation with well-defined hand-off

Device classes

On an I3C bus in its default (SDR) mode, four different classes of devices can be supported:

• I3C Main Master
• I3C Secondary Master
• I3C Slave
• I2C Slave (legacy devices)

High Data Rate (HDR) options

I3C Buses always initialize in SDR mode, to enter HDR mode, the normal I2C compatible Repeated Start and Stop conditions generated by a master are replaced with HDR Restart and HDR Exit signal toggling patterns over the SDA and SCL pins.

HDR modes operate in either Double Data Rate (DDR) or Ternary Symbol modes. These modes can only be on buses under one of two limited configurations:

• A Pure I3C Bus – no I2C devices on the bus
• A Mixed Fast Bus – Where I2C devices on the bus are equipped with a 50 ns Spike Filter

There are three possible HDR modes:

• HDR-DDR Double Data Rate – Data transfers on both clock edges, permitting throughput up to 20 Mbit/s (25 Mbit/s raw bit rate)
• HDR-TSP Ternary Symbol for Pure Bus – Increases throughput by using both SDA and SCL wires for data. Not allowed on mixed I2C–I3C bus.
• HDR-TSL Ternary Symbol for Legacy Bus – Permits buses including I2C devices (with a spike filter) to operate at higher speeds.

I2C features not supported in I3C

• Pull-up resistors are not used, eliminating them improves speed and reduces power consumption
• Clock Stretching – devices are expected to be fast enough to operate at bus speed.
• I2C Extended (10-bit) Addresses. All devices on an I3C bus are addressed by a 7-bit address, and have a unique 48-bit address which is used only during dynamic address assignments.