Engineering:MIPS-X

Short description: none

MIPS-X

Bits	32-bit
Introduced	1987 (1987)
Design	RISC
Predecessor	Stanford MIPS

MIPS-X is a reduced instruction set computer (RISC) microprocessor and instruction set architecture (ISA) developed as a follow-on project to the MIPS project at Stanford University by the same team that developed MIPS. The project was supported by the Defense Advanced Research Projects Agency (DARPA) and began in 1984. Its final form was described in a set of papers released in 1986–87. Unlike its older cousin, MIPS-X was never commercialized as a workstation central processing unit (CPU), and has mainly been seen in embedded system designs based on chips designed by Integrated Information Technology (IIT) for use in digital video applications.

MIPS-X, while designed by the same team and architecturally very similar, is instruction-set incompatible with the mainline MIPS architecture R-series processors. The MIPS-X processor introduced the concept of a delayed branch, which includes two delay slots. An MIPS-X processor also includes a Processor Status Word (PSW) register. The PSW register contains some flags that enable interruptions, overflow exceptions and other status information. The MIPS-X processor is obscure enough that, as of November 20, 2005, support for it is provided only by specialist developers (such as Green Hills Software), and is notably missing from the GNU Compiler Collection (GCC).

MIPS-X has become important among DVD player firmware hackers, since many DVD players (especially low-end devices) use chips based on the IIT design (and produced by ESS Technology), as their central processor. Devices such as the ESS VideoDrive system on a chip (SoC) also include a digital signal processor (DSP) (coprocessor) for decoding MPEG audio and video streams.

External links

• The original MIPS-X paper from Stanford