Engineering:ARM Cortex-A510
From HandWiki
| General Info | |
|---|---|
| Launched | 2021 |
| Designed by | ARM Ltd. |
| Performance | |
| HyperTransport speeds | 2.02 GT/s to unit= unit= GT/s |
| Architecture and classification | |
| Architecture | ARMv9-A |
| Microarchitecture | ARM Cortex-A510 |
| Instruction set | ARMv9-A |
| Products, models, variants | |
| Product code name(s) |
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| History | |
| Predecessor | ARM Cortex-A55 |
The ARM Cortex-A510 is the successor to the ARM Cortex-A55 and the first ARMv9 high efficiency “LITTLE” CPU.[1] It is the companion to the ARM Cortex-A710 "big" core. It's a 64-bit instruction set clean-sheet CPU designed by ARM Holdings' Cambridge design team.[2]
Design:
- 3-wide in-order design, the Cortex-A55 was 2-wide.[3]
- 3-wide fetch and decode front-end as well as 3-wide issue and execute on the back-end,[4] which includes 3 ALU's.[5]
Improvements:
- 35% performance uplift compared to Cortex-A55
- 20% more energy efficient than Cortex-A55
- 3x ML uplift[1]
References
- ↑ 1.0 1.1 "First Armv9 Cortex CPUs for Consumer Compute" (in en). https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/first-armv9-cpu-cores.
- ↑ Frumusanu, Andrei. "Arm Announces Mobile Armv9 CPU Microarchitectures: Cortex-X2, Cortex-A710 & Cortex-A510". https://www.anandtech.com/show/16693/arm-announces-mobile-armv9-cpu-microarchitectures-cortexx2-cortexa710-cortexa510.
- ↑ "Cortex-A510 - Microarchitectures - ARM - WikiChip" (in en). https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a510.
- ↑ "Cortex-A510 - Microarchitectures - ARM - WikiChip" (in en). https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a510.
- ↑ Frumusanu, Andrei. "Arm Announces Mobile Armv9 CPU Microarchitectures: Cortex-X2, Cortex-A710 & Cortex-A510". https://www.anandtech.com/show/16693/arm-announces-mobile-armv9-cpu-microarchitectures-cortexx2-cortexa710-cortexa510.
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