Advanced Matrix Extensions

From HandWiki
Short description: Extensions to the x86 instruction set architecture

Advanced Matrix Extensions (AMX), also known as Intel Advanced Matrix Extensions (Intel AMX), are extensions to the x86 instruction set architecture (ISA) for microprocessors from Intel designed to work on matrices to accelerate artificial intelligence (AI) and machine learning (ML) workloads.[1]

Extensions

AMX was introduced by Intel in June 2020 and first supported by Intel with the Sapphire Rapids microarchitecture for Xeon servers, released in January 2023.[2][3] It introduced 2-dimensional registers called tiles upon which accelerators can perform operations. It is intended as an extensible architecture; the first accelerator implemented is called tile matrix multiply unit (TMUL).[4][5]

In Intel Architecture Instruction Set Extensions and Future Features revision 46, published in September 2022, a new AMX-FP16 extension was documented. This extension adds support for half-precision floating-point numbers. In revision 48 from March 2023, AMX-COMPLEX was documented, adding support for half-precision floating-point complex numbers. Both extensions are planned for inclusion in the future Granite Rapids processors (AMX-COMPLEX - only in Granite Rapids-D[6]).

Tile matrix multiply unit

TMUL unit supports BF16 and INT8 input types.[7] AMX-FP16 also adds support for real and complex FP16 numbers. The register file consists of 8 tiles, each with 16 rows of size of 64 bytes (32 BF16/FP16 or 64 INT8 elements). The only supported operation is matrix multiplication [math]\displaystyle{ C_{nm} += \sum_{j=1}^J A_{nj}B_{jm}. }[/math][4]

4th Gen Intel Xeon Scalable processor can perform 2048 INT8 or 1024 BF16 operations per cycle:[8][9] the maximal input sizes are [math]\displaystyle{ 16 \times J }[/math] for A and [math]\displaystyle{ J \times 16 }[/math] for B, where J is 64 for INT8 and 32 BF16. The matrix multiplication requires [math]\displaystyle{ 256J }[/math] multiplication and [math]\displaystyle{ 256J }[/math] additions, thus performing [math]\displaystyle{ 512J }[/math] operations in 16 cycles.[9]

Software support

References

  1. ↑ Hemsoth, Nicole (August 19, 2021). "With AMX, Intel Adds AI/ML Sparkle to Sapphire Rapids". https://www.nextplatform.com/2021/08/19/with-amx-intel-adds-ai-ml-sparkle-to-sapphire-rapids/. 
  2. ↑ online, heise (28 June 2020). "Intel AMX: Erste Informationen zur Advanced Matrix Extensions Architecture". https://www.heise.de/news/Intel-AMX-Erste-Informationen-zur-Advanced-Matrix-Extensions-Architecture-4797415.html. 
  3. ↑ Cutress, Ian. "Intel Xeon Sapphire Rapids: How To Go Monolithic with Tiles". https://www.anandtech.com/show/16921/intel-sapphire-rapids-nextgen-xeon-scalable-gets-a-tiling-upgrade. 
  4. ↑ 4.0 4.1 "Intel® Architecture Instruction Set Extensions and Future Features". https://www.intel.com/content/www/us/en/content-details/790021/intel-architecture-instruction-set-extensions-programming-reference.html. 
  5. ↑ Schor, David (June 29, 2020). "The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids". https://fuse.wikichip.org/news/3600/the-x86-advanced-matrix-extension-amx-brings-matrix-operations-to-debut-with-sapphire-rapids/. 
  6. ↑ Larabel, Michael (July 12, 2023). "Intel Granite Rapids D Support Merged Into GCC 14". https://www.phoronix.com/news/Granite-Rapids-D-GCC-14. 
  7. ↑ "Advanced Matrix Extension (AMX) - x86 - WikiChip". https://en.wikichip.org/wiki/x86/amx. 
  8. ↑ "Accelerate Artificial Intelligence (AI) Workloads with Intel Advanced Matrix Extensions (Intel AMX)". Intel. https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2022-12/accelerate-ai-with-amx-sb.pdf. 
  9. ↑ 9.0 9.1 "Intel® 64 and IA-32 Architectures Optimization Reference Manual Volume 1". Intel. https://www.intel.com/content/www/us/en/content-details/671488/intel-64-and-ia-32-architectures-optimization-reference-manual-volume-1.html. 
  10. ↑ "What's New in LLVM for 4th Gen Intel® Xeon® & Max Series CPUs". https://www.intel.com/content/www/us/en/developer/articles/technical/whats-new-in-llvm-for-4th-gen-intel-xeon-processor.html. 
  11. ↑ Larabel, Michael (2020-07-02). "Intel AMX Support Begins Landing In LLVM" (in en-US). https://www.phoronix.com/scan.php?page=news_item&px=Intel-AMX-LLVM-Starts. 
  12. ↑ "[X86-64 Support Intel AMX instructions"] (in en-US). 2020-07-02. https://github.com/llvm/llvm-project/commit/aded4f0cc070fcef6763c9a3c2ba764d652b692e. 
  13. ↑ 13.0 13.1 Larabel, Michael (2020-07-02). "Intel AMX Support Lands In The GNU Assembler" (in en-US). https://www.phoronix.com/scan.php?page=news_item&px=Intel-AMX-Gas. 
  14. ↑ "GCC 11 Release Series — Changes, New Features, and Fixes - GNU Project". https://gcc.gnu.org/gcc-11/changes.html. 
  15. ↑ "[PATCH Enable GCC support for AMX"] (in en-US). 2020-07-06. https://gcc.gnu.org/pipermail/gcc-patches/2020-July/549415.html. 
  16. ↑ "Enable GCC support for AMX-TILE,AMX-INT8,AMX-BF16. · gcc-mirror/gcc@5c60984" (in en). https://github.com/gcc-mirror/gcc/commit/5c609842d13a4c9c6be1a10f7980a74d27daeb85. 
  17. ↑ "commits with Intel AMX" (in en-US). 2020-07-02. https://sourceware.org/git/?p=binutils-gdb.git&a=search&st=commit&s=Intel+AMX. 
  18. ↑ "x86: Detect Intel Advanced Matrix Extensions" (in en-US). 2020-07-02. https://sourceware.org/git/?p=glibc.git;a=commit;h=4fdd4d41a17dda26c854ed935658154a17d4b906. 
  19. ↑ "Linux 5.16 Features Include FUTEX2, Intel AMX, Folios, DG2/Alchemist, More Apple Silicon Support". https://www.phoronix.com/review/linux-516-features. 
  20. ↑ "Accessing Sapphire Rapids AMX instructions on vSphere" (in en-US). 2023-08-24. https://earlruby.org/2023/08/accessing-sapphire-rapids-amx-instructions-on-vsphere/. 

External links



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