Engineering:Cache coherent interconnect for accelerators
The cache coherent interconnect for accelerators (CCIX) protocol is the result of an effort of a joint group of computer, hardware and software component vendors: AMD, ARM, Huawei, Mellanox Technologies, Qualcomm and Xilinx.[1]
Quotes from the homepage:
- The mission of the CCIX Consortium is to develop and promote adoption of an industry standard specification to enable coherent interconnect technologies between general-purpose processors and acceleration devices for efficient heterogeneous computing.
- The CCIX standard is available to member companies with initial products expected in 2017.
Current Status
As of 2021, the future of CCIX as widely used interface to attach accelerators to servers in a cache-coherent fashion is doubtful. Many of the original members of the CCIX Consortium have instead opted to support the competing Compute Express Link (CXL) standard, originally developed by Intel but then opened up, for the same purpose. This has led to processors originally announced with CCIX support, such as the AMD Epyc 7002, never actually shipping with that feature enabled. On the side of servers with ARM processors that also list CCIX in their specifications, such as the TaiShan 200 series from Huawei, many do not support the use of CCIX in practice, as it has not been fully validated.
References
- ↑ Jeff Defilippi (October 11, 2016). "How do AMBA, CCIX and GenZ address the needs of the data center?". ARM Community blog. https://community.arm.com/processors/b/blog/posts/how-do-amba-ccix-and-genz-address-the-needs-of-the-data-center.
External links
| General | |
|---|---|
| Standards |
|
| Storage | |
| Peripheral | |
| Audio | |
| Portable | |
| Embedded | |
Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.  Category | |
 |
