Engineering:Epyc

AMD Epyc

General Info
Launched	June 2017
Marketed by	AMD
Designed by	AMD
Common manufacturer(s)	GlobalFoundries (14 nm) TSMC (7 nm)
Performance
Max. CPU clock rate	2.7 GHz to 4.1 GHz
Architecture and classification
Min. feature size	14 nm to 7 nm
Microarchitecture	Zen Zen 2 Zen 3 Zen 4 Zen 4c
Instruction set	x86-64 MMX(+), SSE1, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, AVX2, FMA3, CVT16/F16C, ABM, BMI1, BMI2 AES, CLMUL, RDRAND, SHA, SME AMD-V, AMD-Vi
Physical specifications
Cores	up to 64 cores/128 threads per socket
Socket(s)	SP3, SP5
Products, models, variants
Core name(s)	Naples Rome Milan Genoa Bergamo
Brand name(s)	Epyc
History
Predecessor	Opteron

Epyc is a brand of multi-core x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets. Epyc processors share the same microarchitecture as their regular desktop-grade counterparts, but have enterprise-grade features such as higher core counts, more PCI Express lanes, support for larger amounts of RAM, and larger cache memory. They also support multi-chip and dual-socket system configurations by using the Infinity Fabric interconnect.

History

In March 2017, AMD announced plans to re-enter the server market with a platform based on the Zen microarchitecture, codenamed Naples, and officially revealed it under the brand name Epyc in May. That June, AMD officially launched Epyc 7001 series processors, offering up to 32 cores per socket, and enabling performance that allowed Epyc to be competitive with the competing Intel Xeon product line. Two years later, in August 2019, the Epyc 7002 'Rome' series processors, based on the Zen 2 microarchitecture, launched, doubling the core count per socket to 64, and increasing per-core performance dramatically over the last generation architecture.

In March 2021, AMD launched the Epyc 7003 'Milan' series, based on the Zen 3 microarchitecture. Epyc Milan brought the same 64 cores as Epyc Rome, but with much higher per-core performance, with the EPYC 7763 beating the EPYC 7702 by up to 22% despite having the same number of cores and threads. A refresh of the Epyc 7003 'Milan' series with 3D V-Cache named Milan-X launched March 21st, 2022, using the same cores as Epyc Milan, but with an additional 512MB of cache stacked onto the compute dies, bringing the total amount of cache per CPU to 768 MB.

On November 8th, 2021, AMD unveiled the upcoming generations of AMD EPYC, also unveiling the new LGA-6096 SP5 socket that would support the upcoming generations of Epyc chips. Codenamed Genoa, the first Zen 4 based Epyc CPUs will be built on a TSMC 5nm process node and support up to 96 cores and 192 threads per socket, alongside 12 channels of DDR5, 128 PCIe 5.0 lanes, and Compute Express Link 1.1. AMD also shared information regarding the sister-chip of Genoa, codenamed Bergamo. Bergamo will be based on a modified Zen 4 microarchitecture named Zen 4c, designed to allow for much higher core counts and efficiency at the cost of lower single-core performance, targeting cloud providers and workloads, compared to traditional high performance computing workloads. Bergamo will be compatible with Socket SP5, and will support up to 128 cores and 256 threads per socket.

AMD EPYC CPU Codenames

Gen	Year	Name	Cores
1st	2017	Naples	32 × Zen 1
2nd	2019	Rome	64 × Zen 2
3rd	2021	Milan	64 × Zen 3
	2022	Milan-X	64 x Zen 3
4th	2022	Genoa	96 × Zen 4
	2023	Genoa-X	96 × Zen 4
		Bergamo	128 × Zen 4c
		Siena	64 × Zen 4
5th	2024	Turin
6th	2025	Venice

Design

A delidded second gen Epyc 7702, showing the die configuration

Epyc CPUs use a multi-chip-module design to enable higher yields for a CPU than traditional monolithic dies. First gen Epyc CPUs are composed of four 14 nm compute dies, each with up to 8 cores. Cores are symmetrically disabled on dies to create lower binned products with fewer cores but the same I/O and memory footprint. Second and Third gen Epyc CPUs are composed of eight compute dies built on a 7 nm process node, and a large I/O die built on a 14 nm process node. Third gen Milan-X CPUs use advanced through-silicon-vias to stack an additional die on top of each of the 8 compute dies, adding 64 MB of L3 cache per die.

Epyc supports both single socket and dual socket operation. In a dual socket configuration, 64 PCIe lanes from each CPU are allocated to AMD's proprietary Infinity Fabric interconnect to allow for full bandwidth between both CPUs. As such, a dual socket configuration has the same number of usable PCIe lanes as a single socket configuration. First generation Epyc CPUs had 128 PCIe 3.0 lanes, while second and third generation had 128 PCIe 4.0 lanes. All current Epyc CPUs are equipped with up to eight channels of DDR4 at varying speeds, though next gen Genoa CPUs are confirmed by AMD to support up to twelve channels of DDR5.

Unlike Opteron, Intel equivalents and AMD's desktop processors (excluding Socket AM1), Epyc processors are chipset-free - also known as system on a chip. That means most features required to make servers fully functional (such as memory, PCI Express, SATA controllers, etc.) are fully integrated into the processor, eliminating the need for a chipset to be placed on the mainboard. Some features may require the use of additional controller chips to utilize.

A near-infrared photograph of a delidded second gen Epyc 7702

Reception

Initial reception to Epyc was generally positive. Epyc was generally found to outperform Intel CPUs in cases where the cores could work independently, such as in high-performance computing and big-data applications. First generation Epyc fell behind in database tasks compared to Intel's Xeon parts due to higher cache latency. In 2021, Meta Platforms selected Epyc chips for its metaverse data centers.

Features

CPU features table

Products

Server

First generation Epyc (Naples)

The following table lists the devices using the first generation design.

A "P" suffix denotes support for only a single socket configuration. Non-P models use 64 PCI-E lanes from each processor for the communication between processors.

A first generation Epyc die configuration

An Epyc CPU in an SP3 socket

Second generation Epyc (Rome)

First generation Epyc processor

In November 2018 AMD announced Epyc 2 at their Next Horizon event, the second generation of Epyc processors code-named "Rome" and based on the Zen 2 microarchitecture. The processors feature up to eight 7 nm-based "chiplet" processors with a 14 nm-based IO chip providing 128 PCIe lanes in the center interconnected via Infinity Fabric. The processors support up to 8 channels of DDR4 RAM up to 4 TB, and introduce support for PCIe 4.0. These processors have up to 64 cores with 128 SMT threads per socket. The 7 nm "Rome" is manufactured by TSMC. It was released on August 7, 2019.

The bottom side of an Epyc CPU mounted in a plastic carrier

Third generation Epyc (Milan)

At the HPC-AI Advisory Council in the United Kingdom in October 2019, AMD stated specifications for Milan, Epyc chips based on the Zen 3 microarchitecture. Milan chips will use Socket SP3, with up to 64 cores on package, and support eight channel DDR4 SDRAM and 128 PCIe 4.0 lanes. It also announced plans for the subsequent generation of chips, codenamed Genoa, that will be based on the Zen 4 microarchitecture and use Socket SP5.

Milan CPUs were launched by AMD on 15 March 2021.

Milan-X CPUs were launched March 21st, 2022. Milan-X CPUs use 3D V-Cache technology to increase the maximum L3 cache per socket capacity from 256 MB to 768 MB.

Embedded

First generation Epyc (Snowy Owl)

In February 2018, AMD also announced the EPYC 3000 series of embedded Zen CPUs.

Chinese variants

A variant created for the Chinese server market by an AMD–Chinese joint venture is the Hygon Dhyana system on a chip. It is noted to be a variant of the AMD Epyc, and is so similar that "there is little to no differentiation between the chips". It has been noted that there is "less than 200 lines of new kernel code" for Linux kernel support, and that the Dhyana is "mostly a re-branded Zen CPU for the Chinese server market". Later Benchmarks showed that certain floating point instructions are performing worse and AES is disabled, probably to comply with US export restrictions. Cryptography extensions are replaced by Chinese variants.