Engineering:Co-packaged optics
Co-packaged optics (CPO) is a semiconductor packaging technique in which optical transmitter and receiver components (optical engines) are integrated together with an application-specific integrated circuit (ASIC), such as a network switch chip, in a single package.[1] It replaces the pluggable optical transceiver modules conventionally mounted at the edge of the circuit board and is being developed mainly for data centers in which large amounts of data are transferred between AI accelerators.
Principle
With pluggable modules, the electrical signal has to travel over circuit-board traces several centimetres long from the chip to the module. The driver circuits required for this (SerDes) consume considerable power, and the long traces degrade signal integrity. In CPO the optical components sit directly next to the chip on the same substrate or interposer, so that the electrical paths become very short.[1]
The optical engines are usually based on silicon photonics with microring modulators and integrated photodetectors. Because silicon, as an indirect-bandgap semiconductor, hardly emits light, the lasers are generally implemented as external, replaceable light sources.[1][2] According to a 2024 review, pluggable modules require about 15–20 pJ per transmitted bit, whereas CPO systems require about 5–10 pJ/bit.[1]
History
In 2020, Intel demonstrated a prototype combining a 1.6 Tbit/s silicon-photonics engine with a 12.8 Tbit/s Ethernet switch; in 2022, Broadcom followed with a 25.6 Tbit/s CPO switch.[1] In 2024, Broadcom introduced the 51.2 Tbit/s Bailly switch.[2] In March 2025, Nvidia announced the Quantum-X Photonics (InfiniBand) and Spectrum-X Photonics (Ethernet) switch families, the latter with up to 400 Tbit/s of switching capacity.[3] Nvidia and Broadcom began shipping in 2026; the market research firm TrendForce expects broad adoption in 2027–2028.[4]
Challenges
Bottlenecks include the manufacturing yield of optical engines, limited silicon-photonics production capacity, and competition with AI chips for 2.5D and 3D advanced-packaging capacity.[4] Technical difficulties include heat dissipation at high power density, coupling optical fibers to the very narrow silicon waveguides, and serviceability, since a failed optical port inside the package cannot easily be replaced.[1][2]
See also
References
- ↑ 1.0 1.1 1.2 1.3 1.4 1.5 Tian, W. (2024). "Progress in Research on Co-Packaged Optics". Micromachines 15 (10). doi:10.3390/mi15101211.
- ↑ 2.0 2.1 2.2 Yeluri, Sharada (2025-05-07). "Co-Packaged Optics — a deep dive". https://blog.apnic.net/2025/05/07/co-packaged-optics-a-deep-dive/.
- ↑ "NVIDIA Announces Spectrum-X Photonics, Co-Packaged Optics Networking Switches to Scale AI Factories to Millions of GPUs". Nvidia. 2025-03-18. https://nvidianews.nvidia.com/news/nvidia-spectrum-x-co-packaged-optics-networking-switches-ai-factories.
- ↑ 4.0 4.1 "NVIDIA and Broadcom Begin Volume Ramp of CPO Switches, with Optical Engine Yield and Advanced Packaging Capacity Emerging as Key Expansion Bottlenecks, Says TrendForce". TrendForce. 2026-07-27. https://www.trendforce.com/presscenter/news/20260727-13151.html.
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