Engineering:PA-7100
The PA-7100 is a microprocessor developed by Hewlett-Packard (HP) that implemented the PA-RISC 1.1 instruction set architecture (ISA). It is also known as the PCX-T and by its code name Thunderbird. It was introduced in early 1992 and was the first PA-RISC microprocessor to integrate the floating-point unit (FPU) on-die. It operated at 33 – 100 MHz and competed primarily with the Digital Equipment Corporation (DEC) Alpha 21064 in the workstation and server markets. PA-7100 users were HP in its HP 9000 workstations and Stratus Computer in its Continuum fault-tolerant servers.
It was based on the PA-7000 (PCX-S) chip set, a previous PA-RISC implementation consisting of a microprocessor and FPU. The PA-7100 contains 850 000 transistors and measures 14.3 x 14.3 mm for an area of 204.49 mm². It was fabricated by HP in their CMOS26B process, a 0.8 μm complementary metal–oxide–semiconductor (CMOS) process. The PA-7100 is packaged in a 504-pin ceramic pin grid array that has a copper-tungsten heat spreader.
An improved PA-7100, the PA-7150 was introduced in 1994. It operated at 125 MHz, due to improved circuit design. It was fabricated in the same CMOS26B process as the PA-7100.
Both microprocessors were fabricated at HP's Corvallis, Oregon and Fort Collins, Colorado fabrication plants.[1]
The PA-7100LC and PA-7200 microprocessors were also based on the PA-7100.[2][3]
Notes
References
- "PA-7100 PA-RISC Processor". OpenPA.net. http://www.openpa.net/pa-risc_processor_pa-7100.html.
- Asprey, T.; Averill, G.S.; DeLano, E.; Mason, R.; Weiner, B.; Yetter, J. (June 1993). "Performance features of the PA7100 microprocessor". IEEE Micro 13 (3): 22–35. doi:10.1109/40.216746. https://ieeexplore.ieee.org/document/216746.
- Chan, K.K.; Hay, C.C.; Keller, J.R.; Kurpanek, G.P.; Schumacher, F.X.; Zheng, J. (February 1996). "Design of the HP PA 7200 CPU". Hewlett-Packard Journal 47 (1): 25–33. http://www.hpl.hp.com/hpjournal/96feb/feb96a3.pdf.
- DeLano, E.; Walker, W.; Yetter, J.; Forsyth, M. (1992). "A high speed superscalar PA-RISC processor". Proceedings of Compcon Spring 1992. IEEE. pp. 116–121. doi:10.1109/CMPCON.1992.186696. ISBN 0-8186-2655-0. https://ieeexplore.ieee.org/document/186696.
- DeTar, Jim (20 December 1993). "HP spins PA-RISC architecture; part of five-year roadmap". Electronic News. http://findarticles.com/p/articles/mi_m0EKF/is_n1994_v39/ai_15007968/.
- Gwennap, Linley (7 March 1994). "PA-7200 Enables Inexpensive MP Systems". Microprocessor Report. https://docencia.ac.upc.edu/ETSETB/SEGPAR/microprocessors/pa7200%20(mpr).pdf.
- Heikes, C. (1994). "A 4.5 mm2 multiplier array for a 200 MFLOP pipelined coprocessor". Proceedings of IEEE International Solid-State Circuits Conference — ISSCC '94. IEEE. pp. 290–1. doi:10.1109/ISSCC.1994.344637. ISBN 0-7803-1844-7. https://ieeexplore.ieee.org/document/344637.
- Yetter, J.; Miller, B.; Jaffe, W.; DeLano, E. (1992). "A 100 MHz superscalar PA-RISC CPU/coprocessor chip". 1992 Symposium on VLSI Circuits Digest of Technical Papers. IEEE. pp. 12–13. doi:10.1109/VLSIC.1992.229260. ISBN 0-7803-0701-1. https://ieeexplore.ieee.org/document/229260.
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