Engineering:Transistor model

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Short description: Simulation of physical processes taking place in an electronic device

Transistors are simple devices with complicated behavior[citation needed]. In order to ensure the reliable operation of circuits employing transistors, it is necessary to scientifically model the physical phenomena observed in their operation using transistor models. There exists a variety of different models that range in complexity and in purpose. Transistor models divide into two major groups: models for device design and models for circuit design.

Models for device design

The modern transistor has an internal structure that exploits complex physical mechanisms. Device design requires a detailed understanding of how device manufacturing processes such as ion implantation, impurity diffusion, oxide growth, annealing, and etching affect device behavior. Process models simulate the manufacturing steps and provide a microscopic description of device "geometry" to the device simulator. "Geometry" does not mean readily identified geometrical features such as a planar or wrap-around gate structure, or raised or recessed forms of source and drain (see Figure 1 for a memory device with some unusual modeling challenges related to charging the floating gate by an avalanche process). It also refers to details inside the structure, such as the doping profiles after completion of device processing.

Figure 1: Floating-gate avalanche injection memory device FAMOS

With this information about what the device looks like, the device simulator models the physical processes taking place in the device to determine its electrical behavior in a variety of circumstances: DC current–voltage behavior, transient behavior (both large-signal and small-signal), dependence on device layout (long and narrow versus short and wide, or interdigitated versus rectangular, or isolated versus proximate to other devices). These simulations tell the device designer whether the device process will produce devices with the electrical behavior needed by the circuit designer, and is used to inform the process designer about any necessary process improvements. Once the process gets close to manufacture, the predicted device characteristics are compared with measurement on test devices to check that the process and device models are working adequately.

Although long ago the device behavior modeled in this way was very simple – mainly drift plus diffusion in simple geometries – today many more processes must be modeled at a microscopic level; for example, leakage currents[1] in junctions and oxides, complex transport of carriers including velocity saturation and ballistic transport, quantum mechanical effects, use of multiple materials (for example, Si-SiGe devices, and stacks of different dielectrics) and even the statistical effects due to the probabilistic nature of ion placement and carrier transport inside the device. Several times a year the technology changes and simulations have to be repeated. The models may require change to reflect new physical effects, or to provide greater accuracy. The maintenance and improvement of these models is a business in itself.

These models are very computer intensive, involving detailed spatial and temporal solutions of coupled partial differential equations on three-dimensional grids inside the device.[2][3][4][5][6] Such models are slow to run and provide detail not needed for circuit design. Therefore, faster transistor models oriented toward circuit parameters are used for circuit design.

Models for circuit design

Transistor models are used for almost all modern electronic design work. Analog circuit simulators such as SPICE use models to predict the behavior of a design. Most design work is related to integrated circuit designs which have a very large tooling cost, primarily for the photomasks used to create the devices, and there is a large economic incentive to get the design working without any iterations. Complete and accurate models allow a large percentage of designs to work the first time.

Modern circuits are usually very complex. The performance of such circuits is difficult to predict without accurate computer models, including but not limited to models of the devices used. The device models include effects of transistor layout: width, length, interdigitation, proximity to other devices; transient and DC current–voltage characteristics; parasitic device capacitance, resistance, and inductance; time delays; and temperature effects; to name a few items.[7]

Large-signal nonlinear models

Nonlinear, or large signal transistor models fall into three main types:[8][9]

Physical models

These are models based upon device physics, based upon approximate modeling of physical phenomena within a transistor.[1][10] Parameters[11][12] within these models are based upon physical properties such as oxide thicknesses, substrate doping concentrations, carrier mobility, etc.[13] In the past these models were used extensively, but the complexity of modern devices makes them inadequate for quantitative design. Nonetheless, they find a place in hand analysis (that is, at the conceptual stage of circuit design), for example, for simplified estimates of signal-swing limitations.

Empirical models

This type of model is entirely based upon curve fitting, using whatever functions and parameter values most adequately fit measured data to enable simulation of transistor operation. Unlike a physical model, the parameters in an empirical model need have no fundamental basis, and will depend on the fitting procedure used to find them. The fitting procedure is key to success of these models if they are to be used to extrapolate to designs lying outside the range of data to which the models were originally fitted. Such extrapolation is a hope of such models, but is not fully realized so far.

Small-signal linear models

Small-signal or linear models are used to evaluate stability, gain, noise and bandwidth, both in the conceptual stages of circuit design (to decide between alternative design ideas before computer simulation is warranted) and using computers. A small-signal model is generated by taking derivatives of the current–voltage curves about a bias point or Q-point. As long as the signal is small relative to the nonlinearity of the device, the derivatives do not vary significantly, and can be treated as standard linear circuit elements. An advantage of small signal models is they can be solved directly, while large signal nonlinear models are generally solved iteratively, with possible convergence or stability issues. By simplification to a linear model, the whole apparatus for solving linear equations becomes available, for example, simultaneous equations, determinants, and matrix theory (often studied as part of linear algebra), especially Cramer's rule. Another advantage is that a linear model is easier to think about, and helps to organize thought.

Small-signal parameters

A transistor's parameters represent its electrical properties. Engineers employ transistor parameters in production-line testing and in circuit design. A group of a transistor's parameters sufficient to predict circuit gain, input impedance, and output impedance are components in its small-signal model.

A number of different two-port network parameter sets may be used to model a transistor. These include:

Scattering parameters, or S parameters, can be measured for a transistor at a given bias point with a vector network analyzer. S parameters can be converted to another parameter set using standard matrix algebra operations.

Popular models

See also

References

  1. ↑ 1.0 1.1 , Basil"Semiconductor device simulation method and simulator" patent WO2000077533A3, issued 2001-04-26
  2. ↑ Carlo Jacoboni; Paolo Lugli (1989). The Monte Carlo Method for Semiconductor Device Simulation. Wien: Springer-Verlag. ISBN 3-211-82110-4. https://books.google.com/books?id=3cWnyhKmACEC&dq=isbn&pg=PP1. 
  3. ↑ Siegfried Selberherr (1984). Analysis and Simulation of Semiconductor Devices. Wien: Springer-Verlag. ISBN 3-211-81800-6. https://books.google.com/books?id=EE4HlRZTYi4C&dq=isbn&pg=PA97. 
  4. ↑ Tibor Grasser, ed (2003). Advanced Device Modeling and Simulation (Int. J. High Speed Electron. and Systems). World Scientific. ISBN 981-238-607-6. https://books.google.com/books?id=HBkA3_pZMp4C&q=%22MOSFET++simulation%22. 
  5. ↑ Kramer, Kevin M.; Hitchon, W. Nicholas G. (1997). Semiconductor devices: a simulation approach. Upper Saddle River, NJ: Prentice Hall PTR. ISBN 0-13-614330-X. 
  6. ↑ . Morgan & Claypool. 2006. p. 83. ISBN 1-59829-056-8. https://books.google.com/books?id=DBPnzqy5Fd8C&q=%22gate+tunneling%22. 
  7. ↑ Carlos Galup-Montoro; Mǻrcio C Schneider (2007). Mosfet Modeling for Circuit Analysis And Design. World Scientific. ISBN 978-981-256-810-6. https://books.google.com/books?id=yrrDcRm9bfUC&dq=%22gate+tunneling%22&pg=PA293. 
  8. ↑ Narain Arora (2007). Mosfet Modeling for VLSI Simulation: Theory And Practice. World Scientific. p. Chapter 1. ISBN 978-981-256-862-5. https://books.google.com/books?id=SkT2xOuvpuYC&q=%22table+lookup+model%22. 
  9. ↑ Yannis Tsividis (1999). Operational Modeling of the MOS Transistor (Second ed.). New York: McGraw-Hill. ISBN 0-07-065523-5. https://archive.org/details/isbn_9780073032313. 
  10. ↑ Lui, Basil; Migliorato, P (1997-04-01). "A new generation-recombination model for device simulation including the Poole-Frenkel effect and phonon-assisted tunnelling" (in en). Solid-State Electronics 41 (4): 575–583. doi:10.1016/S0038-1101(96)00148-7. ISSN 0038-1101. Bibcode: 1997SSEle..41..575L. https://www.sciencedirect.com/science/article/pii/S0038110196001487. 
  11. ↑ Lui, Basil; Tam, S. W. B.; Migliorato, P. (1998). "A Polysilicon Tft Parameter Extractor" (in en). MRS Online Proceedings Library 507: 365. doi:10.1557/PROC-507-365. ISSN 0272-9172. https://www.cambridge.org/core/journals/mrs-online-proceedings-library-archive/article/abs/polysilicon-tft-parameter-extractor/AFB82CB806F1140E9249C5FA90285B66. 
  12. ↑ Kimura, Mutsumi; Nozawa, Ryoichi; Inoue, Satoshi; Shimoda, Tatsuya; Lui, Basil; Tam, Simon Wing-Bun; Migliorato, Piero (2001-09-01). "Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary for Polycrystalline Silicon Thin-Film Transistors" (in en). Japanese Journal of Applied Physics 40 (9R): 5227. doi:10.1143/JJAP.40.5227. ISSN 1347-4065. Bibcode: 2001JaJAP..40.5227K. https://iopscience.iop.org/article/10.1143/JJAP.40.5227/meta. 
  13. ↑ Lui, Basil; Tam, S. W.-B.; Migliorato, P.; Shimoda, T. (2001-06-01). "Method for the determination of bulk and interface density of states in thin-film transistors". Journal of Applied Physics 89 (11): 6453–6458. doi:10.1063/1.1361244. ISSN 0021-8979. Bibcode: 2001JAP....89.6453L. https://aip.scitation.org/doi/abs/10.1063/1.1361244. 

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