SHA instruction set

From HandWiki
Short description: Extensions to the x86 instruction set architecture

A SHA instruction set is a set of extensions to the ARM, Power, RISC-V and x86 instruction set architecture which support hardware acceleration of the Secure Hash Algorithm (SHA) family.

ARM

SHA-1 and SHA-256 instructions appeared as optional features (FEAT_SHA1 and FEAT_SHA256) in the Arm V8.0 architecture introduced in 2011.[1] The instructions are:

  • SHA-1: SHA1C, SHA1H, SHA1M, SHA1P, SHA1SU0, SHA1SU1
  • SHA-256: SHA256H, SHA256H2, SHA256SU0, SHA256SU1

SHA-512 and SHA-3 instructions appeared as optional features (FEAT_SHA512 and FEAT_SHA3) in the Arm V8.2 architecture. [2] The instructions are:

  • SHA-512: SHA512H, SHA512H2, SHA512SU0, SHA512SU1
  • SHA-3: EOR3, RAX1, XAR, BCAX

A scalable vector extension (SVE) version of the SHA-3 instructions appeared as an optional feature (FEAT_SVE_SHA3) in the Arm V9.0 architecture. [3]

Power

Vector instructions for the Sigma functions for SHA-256 (vshasigmaw) and SHA-512 (vshasigmad) were added in the specification for Power ISA v.2.07[4] released in May 2013. The same instruction performs either Σ₀, Σ₁, σ₀ or σ₁ as described in the SHA-2 standard (FIPS-180-4) depending on parameters.

RISC-V

SHA2 instructions are part of the Zknh extension part of the RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions[5] ratified in November 2021[6].

As SHA-512 is defined on 64-bit words, the instructions for SHA-512 differ in RV32 and RV64, with some RV32 instructions for SHA-512 split the elementary sigma operations in half in order to operate on a single 32-bit register.

The instructions are:

  • SHA-256 (RV32 and RV64): sha256sig0 (SHA-256 σ₀), sha256sig1 (SHA-256 σ₁), sha256sum0 (SHA-256 Σ₀), sha256sum1 (SHA-256 Σ₁)
  • SHA-512 (RV32): sha512sig0h (high half of SHA-512 σ₀), sha512sig0l (low half of SHA-512 σ₀), sha512sig1h (high half of SHA-512 σ₁), sha512sig1l (low half of SHA-512 σ₁), sha512sum0r (SHA-512 Σ₀), sha512sum1r (SHA-512 Σ₁)
  • SHA-512 (RV64): sha512sig0 (SHA-512 σ₀), sha512sig1 (SHA-512 σ₁), sha512sum0 (SHA-512 Σ₀), sha512sum1 (SHA-512 Σ₁)

x86 architecture processors

The original SSE-based extensions added four instructions supporting SHA-1 and three for SHA-256 and were specified in 2013 by Intel.[7] Instructions for SHA-512 were introduced in Arrow Lake and Lunar Lake in 2024.

  • SHA-1: SHA1RNDS4, SHA1NEXTE, SHA1MSG1, SHA1MSG2
  • SHA-256: SHA256RNDS2, SHA256MSG1, SHA256MSG2

The newer SHA-512 instruction set comprises AVX-based versions of the original SHA instruction set marked with a V prefix and these three new AVX-based instructions for SHA-512:

  • VSHA512RNDS2, VSHA512MSG1, VSHA512MSG2

AMD

All recent AMD processors support the original SHA instruction set:

  • AMD Zen[8] (2017) and later processors.

Intel

The following Intel processors support the original SHA instruction set:

  • Intel Goldmont[9] (2016) and later Atom microarchitecture processors.
  • Intel Cannon Lake[10] (2018/2019), Ice Lake[11] (2019) and later processors for laptops ("mainstream mobile").
  • Intel Rocket Lake (2021) and later processors for desktop computers.

The following Intel processors support the newer SHA-512 instruction set:

References

  1. ↑ "The Armv8.0 architecture extension". https://developer.arm.com/documentation/109697/2025_09/Feature-descriptions/The-Armv8-0-architecture-extension?lang=en. 
  2. ↑ "The Armv8.2 architecture extension". https://developer.arm.com/documentation/109697/2025_09/Feature-descriptions/The-Armv8-2-architecture-extension?lang=en. 
  3. ↑ "The Armv9.0 architecture extension". https://developer.arm.com/documentation/109697/2025_09/Feature-descriptions/The-Armv9-0-architecture-extension?lang=en#md457-the-armv90-architecture-extension__feat_FEAT_SVE_SHA3. 
  4. ↑ "Power ISA Version 2.07". Power.org. 2013-05-15. https://fileadmin.cs.lth.se/cs/education/EDAN25/PowerISA_V2.07_PUBLIC.pdf. 
  5. ↑ "Zknh - NIST Suite: Hash Function Instructions". RISC-V International. https://docs.riscv.org/reference/isa/v20260120/unpriv/scalar-crypto.html#zknh. 
  6. ↑ "Ratified Extensions". https://riscv.atlassian.net/wiki/spaces/HOME/pages/16154732/Ratified+Extensions. 
  7. ↑ "New Instructions Supporting the Secure Hash Algorithm on Intel® Architecture Processors" (in en). https://software.intel.com/en-us/articles/intel-sha-extensions. 
  8. ↑ "Zen - Microarchitectures - AMD - WikiChip" (in en). https://en.wikichip.org/wiki/amd/microarchitectures/zen#New_instructions. 
  9. ↑ "Goldmont - Microarchitectures - Intel - WikiChip" (in en). https://en.wikichip.org/wiki/intel/microarchitectures/goldmont#New_instructions. 
  10. ↑ "Cannon Lake - Microarchitectures - Intel - WikiChip" (in en). https://en.wikichip.org/wiki/intel/microarchitectures/cannon_lake#New_instructions. 
  11. ↑ "Ice Lake (client) - Microarchitectures - Intel - WikiChip" (in en). https://en.wikichip.org/wiki/intel/microarchitectures/ice_lake_(client)#New_instructions. 

Template:AMD

Template:Instruction set extensions



Retrieved from "https://handwiki.org/wiki/index.php?title=SHA_instruction_set&oldid=4633213"