AI accelerator

From HandWiki
Short description: Hardware acceleration unit for artificial intelligence tasks


An AI accelerator, deep learning processor, or neural processing unit is a class of specialized hardware accelerator[1] or computer system[2][3] designed to accelerate artificial intelligence and machine learning applications, including artificial neural networks and machine vision. Typical applications include algorithms for robotics, Internet of Things, and other data-intensive or sensor-driven tasks.[4] They are often manycore designs and generally focus on low-precision arithmetic, novel dataflow architectures or in-memory computing capability. (As of 2024), a typical AI integrated circuit chip contains tens of billions of MOSFET transistors.[5]

AI accelerators are used in mobile devices, such as neural processing units (NPUs) in Apple iPhones[6] or Huawei cellphones,[7] and personal computers such as Apple silicon Macs, to cloud computing servers such as tensor processing units (TPU) in the Google Cloud Platform.[8] A number of vendor-specific terms exist for devices in this category, and it is an emerging technology without a dominant design.

History

Computer systems have frequently complemented the CPU with special-purpose accelerators for specialized tasks, known as coprocessors. Notable application-specific hardware units include video cards for graphics, sound cards, graphics processing units and digital signal processors. As deep learning and artificial intelligence workloads rose in prominence in the 2010s, specialized hardware units were developed or adapted from existing products to accelerate these tasks.

Early attempts

First attempts like Intel's ETANN 80170NX incorporated analog circuits to compute neural functions.[9]

Later all-digital chips like the Nestor/Intel Ni1000 followed. As early as 1993, digital signal processors were used as neural network accelerators to accelerate optical character recognition software.[10]

By 1988, Wei Zhang et al. had discussed fast optical implementations of convolutional neural networks for alphabet recognition.[11][12]

In the 1990s, there were also attempts to create parallel high-throughput systems for workstations aimed at various applications, including neural network simulations.[13][14]

This presentation covers a past attempt at neural net accelerators, notes the similarity to the modern SLI GPGPU processor setup, and argues that general purpose vector accelerators are the way forward (in relation to RISC-V hwacha project. Argues that NN's are just dense and sparse matrices, one of several recurring algorithms)[15]

FPGA-based accelerators were also first explored in the 1990s for both inference and training.[16][17]

In 2014, Chen et al. proposed DianNao (Chinese for "electric brain"),[18] to accelerate deep neural networks especially. DianNao provides the 452 Gop/s peak performance (of key operations in deep neural networks) only in a small footprint of 3.02 mm2 and 485 mW. Later, the successors (DaDianNao,[19] ShiDianNao,[20] PuDianNao[21]) are proposed by the same group, forming the DianNao Family[22]

Smartphones began incorporating AI accelerators starting with the Qualcomm Snapdragon 820 in 2015.[23][24]

Heterogeneous computing

Heterogeneous computing incorporates many specialized processors in a single system, or a single chip, each optimized for a specific type of task. Architectures such as the Cell microprocessor[25] have features significantly overlapping with AI accelerators including: support for packed low precision arithmetic, dataflow architecture, and prioritizing throughput over latency. The Cell microprocessor has been applied to a number of tasks[26][27][28] including AI.[29][30][31]

In the 2000s, CPUs also gained increasingly wide SIMD units, driven by video and gaming workloads; as well as support for packed low-precision data types.[32] Due to the increasing performance of CPUs, they are also used for running AI workloads. CPUs are superior for DNNs with small or medium-scale parallelism, for sparse DNNs and in low-batch-size scenarios.

Use of GPU

Graphics processing units or GPUs are specialized hardware for the manipulation of images and calculation of local image properties. The mathematical basis of neural networks and image manipulation are similar, embarrassingly parallel tasks involving matrices, leading GPUs to become increasingly used for machine learning tasks.[33][34]

In 2012, Alex Krizhevsky adopted two GPUs to train a deep learning network, i.e., AlexNet,[35] which won the champion of the ISLVRC-2012 competition. During the 2010's, GPU manufacturers such as Nvidia added deep learning related features in both hardware (e.g., INT8 operators) and software (e.g., cuDNN Library).

GPUs continue to be used in large-scale AI applications. For example, Summit, a supercomputer from IBM for Oak Ridge National Laboratory,[36] contains 27,648 Nvidia Tesla V100 cards, which can be used to accelerate deep learning algorithms.

Over the 2010's GPUs continued to evolve in a direction to facilitate deep learning, both for training and inference in devices such as self-driving cars.[37][38] GPU developers such as Nvidia NVLink are developing additional connective capability for the kind of dataflow workloads AI benefits from. As GPUs have been increasingly applied to AI acceleration, GPU manufacturers have incorporated neural network-specific hardware to further accelerate these tasks.[39][40] Tensor cores are intended to speed up the training of neural networks.[40]

Use of FPGAs

Deep learning frameworks are still evolving, making it hard to design custom hardware. Reconfigurable devices such as field-programmable gate arrays (FPGA) make it easier to evolve hardware, frameworks, and software alongside each other.[41][16][17][42]

Microsoft has used FPGA chips to accelerate inference for real-time deep learning services.[43]

Emergence of dedicated AI accelerator ASICs

While GPUs and FPGAs perform far better than CPUs for AI-related tasks, a factor of up to 10 in efficiency[44][45] may be gained with a more specific design, via an application-specific integrated circuit (ASIC).[citation needed] These accelerators employ strategies such as optimized memory use[citation needed] and the use of lower precision arithmetic to accelerate calculation and increase throughput of computation.[46][47] Some low-precision floating-point formats used for AI acceleration are half-precision and the bfloat16 floating-point format.[48][49][50][51][52][53][54] Companies such as Google, Qualcomm, Amazon, Apple, Facebook, AMD and Samsung are all designing their own AI ASICs.[55][56][57][58][59][60] Cerebras Systems has built a dedicated AI accelerator based on the largest processor in the industry, the second-generation Wafer Scale Engine (WSE-2), to support deep learning workloads.[61][62]

Ongoing research

In-memory computing architectures

In June 2017, IBM researchers announced an architecture in contrast to the Von Neumann architecture based on in-memory computing and phase-change memory arrays applied to temporal correlation detection, intending to generalize the approach to heterogeneous computing and massively parallel systems.[63] In October 2018, IBM researchers announced an architecture based on in-memory processing and modeled on the human brain's synaptic network to accelerate deep neural networks.[64] The system is based on phase-change memory arrays.[65]

In-memory computing with analog resistive memories

In 2019, researchers from Politecnico di Milano found a way to solve systems of linear equations in a few tens of nanoseconds via a single operation. Their algorithm is based on in-memory computing with analog resistive memories which performs with high efficiencies of time and energy, via conducting matrix–vector multiplication in one step using Ohm's law and Kirchhoff's law. The researchers showed that a feedback circuit with cross-point resistive memories can solve algebraic problems such as systems of linear equations, matrix eigenvectors, and differential equations in just one step. Such an approach improves computational times drastically in comparison with digital algorithms.[66]

Atomically thin semiconductors

In 2020, Marega et al. published experiments with a large-area active channel material for developing logic-in-memory devices and circuits based on floating-gate field-effect transistors (FGFETs).[67] Such atomically thin semiconductors are considered promising for energy-efficient machine learning applications, where the same basic device structure is used for both logic operations and data storage. The authors used two-dimensional materials such as semiconducting molybdenum disulphide to precisely tune FGFETs as building blocks in which logic operations can be performed with the memory elements. [67]

Integrated photonic tensor core

In 1988, Wei Zhang et al. discussed fast optical implementations of convolutional neural networks for alphabet recognition.[11][12] In 2021, J. Feldmann et al. proposed an integrated photonic hardware accelerator for parallel convolutional processing.[68] The authors identify two key advantages of integrated photonics over its electronic counterparts: (1) massively parallel data transfer through wavelength division multiplexing in conjunction with frequency combs, and (2) extremely high data modulation speeds.[68] Their system can execute trillions of multiply-accumulate operations per second, indicating the potential of integrated photonics in data-heavy AI applications.[68]

Nomenclature

As of 2016, the field is still in flux and vendors are pushing their own marketing term for what amounts to an "AI accelerator", in the hope that their designs and APIs will become the dominant design. There is no consensus on the boundary between these devices, nor the exact form they will take; however several examples clearly aim to fill this new space, with a fair amount of overlap in capabilities.

In the past when consumer graphics accelerators emerged, the industry eventually adopted Nvidia's self-assigned term, "the GPU",[69] as the collective noun for "graphics accelerators", which had taken many forms before settling on an overall pipeline implementing a model presented by Direct3D.

All models of Intel Meteor Lake processors have a Versatile Processor Unit (VPU) built-in for accelerating inference for computer vision and deep learning.[70]

Deep Learning Processors (DLP)

Inspired from the pioneer work of DianNao Family, many DLPs are proposed in both academia and industry with design optimized to leverage the features of deep neural networks for high efficiency. Only at ISCA 2016, three sessions, 15% (!) of the accepted papers, are all architecture designs about deep learning. Such efforts include Eyeriss (MIT),[71] EIE (Stanford),[72] Minerva (Harvard),[73] Stripes (University of Toronto) in academia,[74] TPU (Google),[75] and MLU (Cambricon) in industry.[76] We listed several representative works in Table 1.

Table 1. Typical DLPs
Year DLPs Institution Type Computation Memory Hierarchy Control Peak Performance
2014 DianNao[18] ICT, CAS digital vector MACs scratchpad VLIW 452 Gops (16-bit)
DaDianNao[19] ICT, CAS digital vector MACs scratchpad VLIW 5.58 Tops (16-bit)
2015 ShiDianNao[20] ICT, CAS digital scalar MACs scratchpad VLIW 194 Gops (16-bit)
PuDianNao[21] ICT, CAS digital vector MACs scratchpad VLIW 1,056 Gops (16-bit)
2016 DnnWeaver Georgia Tech digital Vector MACs scratchpad - -
EIE[72] Stanford digital scalar MACs scratchpad - 102 Gops (16-bit)
Eyeriss[71] MIT digital scalar MACs scratchpad - 67.2 Gops (16-bit)
Prime[77] UCSB hybrid Process-in-Memory ReRAM - -
2017 TPU[75] Google digital scalar MACs scratchpad CISC 92 Tops (8-bit)
PipeLayer[78] U of Pittsburgh hybrid Process-in-Memory ReRAM -
FlexFlow ICT, CAS digital scalar MACs scratchpad - 420 Gops ()
DNPU[79] KAIST digital scalar MACS scratchpad - 300 Gops(16bit)

1200 Gops(4bit)

2018 MAERI Georgia Tech digital scalar MACs scratchpad -
PermDNN City University of New York digital vector MACs scratchpad - 614.4 Gops (16-bit)
UNPU[80] KAIST digital scalar MACs scratchpad - 345.6 Gops(16bit)

691.2 Gops(8b) 1382 Gops(4bit) 7372 Gops(1bit)

2019 FPSA Tsinghua hybrid Process-in-Memory ReRAM -
Cambricon-F ICT, CAS digital vector MACs scratchpad FISA 14.9 Tops (F1, 16-bit)

956 Tops (F100, 16-bit)

Digital DLPs

The major components of DLPs architecture usually include a computation component, the on-chip memory hierarchy, and the control logic that manages the data communication and computing flows.

Regarding the computation component, as most operations in deep learning can be aggregated into vector operations, the most common ways for building computation components in digital DLPs are the MAC-based (multiplier-accumulation) organization, either with vector MACs[18][19][21] or scalar MACs.[75][20][71] Rather than SIMD or SIMT in general processing devices, deep learning domain-specific parallelism is better explored on these MAC-based organizations. Regarding the memory hierarchy, as deep learning algorithms require high bandwidth to provide the computation component with sufficient data, DLPs usually employ a relatively larger size (tens of kilobytes or several megabytes) on-chip buffer but with dedicated on-chip data reuse strategy and data exchange strategy to alleviate the burden for memory bandwidth. For example, DianNao, 16 16-in vector MAC, requires 16 × 16 × 2 = 512 16-bit data, i.e., almost 1024GB/s bandwidth requirements between computation components and buffers. With on-chip reuse, such bandwidth requirements are reduced drastically.[18] Instead of the widely used cache in general processing devices, DLPs always use scratchpad memory as it could provide higher data reuse opportunities by leveraging the relatively regular data access pattern in deep learning algorithms. Regarding the control logic, as the deep learning algorithms keep evolving at a dramatic speed, DLPs start to leverage dedicated ISA (instruction set architecture) to support the deep learning domain flexibly. At first, DianNao used a VLIW-style instruction set where each instruction could finish a layer in a DNN. Cambricon[81] introduces the first deep learning domain-specific ISA, which could support more than ten different deep learning algorithms. TPU also reveals five key instructions from the CISC-style ISA.

Hybrid DLPs

Hybrid DLPs emerge for DNN inference and training acceleration because of their high efficiency. Processing-in-memory (PIM) architectures are one most important type of hybrid DLP. The key design concept of PIM is to bridge the gap between computing and memory, with the following manners: 1) Moving computation components into memory cells, controllers, or memory chips to alleviate the memory wall issue.[78][82][83] Such architectures significantly shorten data paths and leverage much higher internal bandwidth, hence resulting in attractive performance improvement. 2) Build high efficient DNN engines by adopting computational devices. In 2013, HP Lab demonstrated the astonishing capability of adopting ReRAM crossbar structure for computing.[84] Inspiring by this work, tremendous work are proposed to explore the new architecture and system design based on ReRAM,[77][85][86][78] phase change memory,[82][87][88] etc.

Benchmarks

Benchmarks such as MLPerf and others may be used to evaluate the performance of AI accelerators.[89] Table 2 lists several typical benchmarks for AI accelerators.

Table 2. Benchmarks.
Year NN Benchmark Affiliations # of microbenchmarks # of component benchmarks # of application benchmarks
2012 BenchNN ICT, CAS N/A 12 N/A
2016 Fathom Harvard N/A 8 N/A
2017 BenchIP ICT, CAS 12 11 N/A
2017 DAWNBench Stanford 8 N/A N/A
2017 DeepBench Baidu 4 N/A N/A
2018 MLPerf Harvard, Intel, and Google, etc. N/A 7 N/A
2019 AIBench ICT, CAS and Alibaba, etc. 12 16 2
2019 NNBench-X UCSB N/A 10 N/A

Potential applications

See also

References

  1. ↑ "Intel unveils Movidius Compute Stick USB AI Accelerator". July 21, 2017. https://www.v3.co.uk/v3-uk/news/3014293/intel-unveils-movidius-compute-stick-usb-ai-accelerator. 
  2. ↑ "Inspurs unveils GX4 AI Accelerator". June 21, 2017. https://insidehpc.com/2017/06/inspurs-unveils-gx4-ai-accelerator/. 
  3. ↑ Wiggers, Kyle (November 6, 2019), Neural Magic raises $15 million to boost AI inferencing speed on off-the-shelf processors, https://venturebeat.com/2019/11/06/neural-magic-raises-15-million-to-boost-ai-training-speed-on-off-the-shelf-processors/, retrieved March 14, 2020 
  4. ↑ "Google Designing AI Processors". https://www.eetimes.com/google-designing-ai-processors/.  Google using its own AI accelerators.
  5. ↑ Moss, Sebastian (2022-03-23). "Nvidia reveals new Hopper H100 GPU, with 80 billion transistors". https://www.datacenterdynamics.com/en/news/nvidia-reveals-new-hopper-h100-gpu-with-80-billion-transistors/. 
  6. ↑ "Deploying Transformers on the Apple Neural Engine" (in en-US). https://machinelearning.apple.com/research/neural-engine-transformers. 
  7. ↑ "HUAWEI Reveals the Future of Mobile AI at IFA". https://consumer.huawei.com/en/press/news/2017/ifa2017-kirin970. 
  8. ↑ Jouppi, Norman P. et al. (2017-06-24). "In-Datacenter Performance Analysis of a Tensor Processing Unit" (in EN). ACM SIGARCH Computer Architecture News 45 (2): 1–12. doi:10.1145/3140659.3080246. 
  9. ↑ Dvorak, J.C. (29 May 1990). "Inside Track". PC Magazine. https://archive.org/details/PC_Magazine_1990_05_29_v9n10/page/n83/mode/2up. 
  10. ↑ "convolutional neural network demo from 1993 featuring DSP32 accelerator". https://www.youtube.com/watch?v=FwFduRA_L6Q. 
  11. ↑ 11.0 11.1 Zhang, Wei (1988). "Shift-invariant pattern recognition neural network and its optical architecture". Proceedings of Annual Conference of the Japan Society of Applied Physics. 
  12. ↑ 12.0 12.1 Zhang, Wei (1990). "Parallel distributed processing model with local space-invariant interconnections and its optical architecture". Applied Optics 29 (32): 4790–7. doi:10.1364/AO.29.004790. PMID 20577468. Bibcode: 1990ApOpt..29.4790Z. 
  13. ↑ Asanović, K.; Beck, J.; Feldman, J.; Morgan, N.; Wawrzynek, J. (January 1994). "Designing a connectionist network supercomputer". International Journal of Neural Systems (ResearchGate) 4 (4): 317-26. doi:10.1142/S0129065793000250. https://www.researchgate.net/publication/15149042_Designing_a_connectionist_network_supercomputer. Retrieved 26 December 2023. 
  14. ↑ "The end of general purpose computers (not)". https://www.youtube.com/watch?v=VtJthbiiTBQ. 
  15. ↑ Ramacher, U.; Raab, W.; Hachmann, J.A.U.; Beichter, J.; Bruls, N.; Wesseling, M.; Sicheneder, E.; Glass, J. et al. (1995). Proceedings of 9th International Parallel Processing Symposium. pp. 774–781. doi:10.1109/IPPS.1995.395862. ISBN 978-0-8186-7074-9. 
  16. ↑ 16.0 16.1 "Space Efficient Neural Net Implementation". ResearchGate. February 1995. https://www.researchgate.net/publication/2318589_Space_Efficient_Neural_Net_Implementation. 
  17. ↑ 17.0 17.1 Gschwind, M.; Salapura, V.; Maischberger, O. (1996). "A Generic Building Block for Hopfield Neural Networks with On-Chip Learning". 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96. pp. 49–52. doi:10.1109/ISCAS.1996.598474. ISBN 0-7803-3073-0. 
  18. ↑ 18.0 18.1 18.2 18.3 Chen, Tianshi; Du, Zidong; Sun, Ninghui; Wang, Jia; Wu, Chengyong; Chen, Yunji; Temam, Olivier (2014-04-05). "DianNao". ACM SIGARCH Computer Architecture News 42 (1): 269–284. doi:10.1145/2654822.2541967. ISSN 0163-5964. 
  19. ↑ 19.0 19.1 19.2 Chen, Yunji; Luo, Tao; Liu, Shaoli; Zhang, Shijin; He, Liqiang; Wang, Jia; Li, Ling; Chen, Tianshi et al. (December 2014). "DaDianNao: A Machine-Learning Supercomputer". 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture. IEEE. pp. 609–622. doi:10.1109/micro.2014.58. ISBN 978-1-4799-6998-2. 
  20. ↑ 20.0 20.1 20.2 Du, Zidong; Fasthuber, Robert; Chen, Tianshi; Ienne, Paolo; Li, Ling; Luo, Tao; Feng, Xiaobing; Chen, Yunji et al. (2016-01-04). "ShiDianNao". ACM SIGARCH Computer Architecture News 43 (3S): 92–104. doi:10.1145/2872887.2750389. ISSN 0163-5964. 
  21. ↑ 21.0 21.1 21.2 Liu, Daofu; Chen, Tianshi; Liu, Shaoli; Zhou, Jinhong; Zhou, Shengyuan; Teman, Olivier; Feng, Xiaobing; Zhou, Xuehai et al. (2015-05-29). "PuDianNao". ACM SIGARCH Computer Architecture News 43 (1): 369–381. doi:10.1145/2786763.2694358. ISSN 0163-5964. 
  22. ↑ Chen, Yunji; Chen, Tianshi; Xu, Zhiwei; Sun, Ninghui; Temam, Olivier (2016-10-28). "DianNao family". Communications of the ACM 59 (11): 105–112. doi:10.1145/2996864. ISSN 0001-0782. 
  23. ↑ "Qualcomm Helps Make Your Mobile Devices Smarter With New Snapdragon Machine Learning Software Development Kit". https://www.qualcomm.com/news/releases/2016/05/02/qualcomm-helps-make-your-mobile-devices-smarter-new-snapdragon-machine. 
  24. ↑ Rubin, Ben Fox. "Qualcomm's Zeroth platform could make your smartphone much smarter" (in en). https://www.cnet.com/tech/mobile/qualcomms-zeroth-platform-could-make-your-smartphone-much-smarter/. 
  25. ↑ Gschwind, Michael; Hofstee, H. Peter; Flachs, Brian; Hopkins, Martin; Watanabe, Yukio; Yamazaki, Takeshi (2006). "Synergistic Processing in Cell's Multicore Architecture". IEEE Micro 26 (2): 10–24. doi:10.1109/MM.2006.41. 
  26. ↑ De Fabritiis, G. (2007). "Performance of Cell processor for biomolecular simulations". Computer Physics Communications 176 (11–12): 660–664. doi:10.1016/j.cpc.2007.02.107. Bibcode: 2007CoPhC.176..660D. 
  27. ↑ Video Processing and Retrieval on Cell architecture. 
  28. ↑ Benthin, Carsten; Wald, Ingo; Scherbaum, Michael; Friedrich, Heiko (2006). 2006 IEEE Symposium on Interactive Ray Tracing. pp. 15–23. doi:10.1109/RT.2006.280210. ISBN 978-1-4244-0693-7. 
  29. ↑ "Development of an artificial neural network on a heterogeneous multicore architecture to predict a successful weight loss in obese individuals". https://www.teco.edu/~scholz/papers/ScholzDiploma.pdf. 
  30. ↑ Kwon, Bomjun; Choi, Taiho; Chung, Heejin; Kim, Geonho (2008). 2008 5th IEEE Consumer Communications and Networking Conference. pp. 1030–1034. doi:10.1109/ccnc08.2007.235. ISBN 978-1-4244-1457-4. 
  31. ↑ Duan, Rubing; Strey, Alfred (2008). Euro-Par 2008 – Parallel Processing. Lecture Notes in Computer Science. 5168. pp. 665–675. doi:10.1007/978-3-540-85451-7_71. ISBN 978-3-540-85450-0. 
  32. ↑ "Improving the performance of video with AVX". February 8, 2012. https://software.intel.com/content/www/us/en/develop/articles/improving-the-compute-performance-of-video-processing-software-using-avx-advanced-vector-extensions-instructions.html. 
  33. ↑ "High Performance Convolutional Neural Networks for Document Processing". 10th International Workshop on Frontiers in Handwriting Recognition. 23 October 2006. https://inria.hal.science/inria-00112631/document. 
  34. ↑ Krizhevsky, A.; Sutskever, I.; Hinton, G.E. (24 May 2017). "ImageNet Classification with Deep Convolutional Neural Networks". Communications of the ACM 60 (6): 84–90. doi:10.1145/3065386. https://dl.acm.org/doi/10.1145/3065386. Retrieved 23 December 2023. 
  35. ↑ Krizhevsky, Alex; Sutskever, Ilya; Hinton, Geoffrey E (2017-05-24). "ImageNet classification with deep convolutional neural networks" (in EN). Communications of the ACM 60 (6): 84–90. doi:10.1145/3065386. 
  36. ↑ "Summit: Oak Ridge National Laboratory's 200 petaflop supercomputer". United States Department of Energy. 2024. https://www.olcf.ornl.gov/olcf-resources/compute-systems/summit. 
  37. ↑ Roe, R. (17 May 2023). "Nvidia in the Driver's Seat for Deep Learning". insideHPC. https://insidehpc.com/2016/05/nvidia-driving-the-development-of-deep-learning. 
  38. ↑ Bohn, D. (5 January 2016). "Nvidia announces 'supercomputer' for self-driving cars at CES 2016". Vox Media. https://www.theverge.com/2016/1/4/10712634/nvidia-drive-px2-self-driving-car-supercomputer-announces-ces-2016. 
  39. ↑ "A Survey on Optimized Implementation of Deep Learning Models on the NVIDIA Jetson Platform", 2019
  40. ↑ 40.0 40.1 Harris, Mark (May 11, 2017). "CUDA 9 Features Revealed: Volta, Cooperative Groups and More". https://developer.nvidia.com/blog/cuda-9-features-revealed/. 
  41. ↑ Sefat, Md Syadus; Aslan, Semih; Kellington, Jeffrey W; Qasem, Apan (August 2019). "Accelerating HotSpots in Deep Neural Networks on a CAPI-Based FPGA". 2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS). pp. 248–256. doi:10.1109/HPCC/SmartCity/DSS.2019.00048. ISBN 978-1-7281-2058-4. https://ieeexplore.ieee.org/document/8855410. 
  42. ↑ "FPGA Based Deep Learning Accelerators Take on ASICs". August 23, 2016. http://www.nextplatform.com/2016/08/23/fpga-based-deep-learning-accelerators-take-asics/. 
  43. ↑ "Microsoft unveils Project Brainwave for real-time AI". 22 August 2017. https://www.microsoft.com/en-us/research/blog/microsoft-unveils-project-brainwave/. 
  44. ↑ "Google boosts machine learning with its Tensor Processing Unit". May 19, 2016. https://techreport.com/news/30155/google-boosts-machine-learning-with-its-tensor-processing-unit/. 
  45. ↑ "Chip could bring deep learning to mobile devices". February 3, 2016. https://www.sciencedaily.com/releases/2016/02/160203134840.htm. 
  46. ↑ "Deep Learning with Limited Numerical Precision". http://proceedings.mlr.press/v37/gupta15.pdf. 
  47. ↑ Rastegari, Mohammad; Ordonez, Vicente; Redmon, Joseph; Farhadi, Ali (2016). "XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks". arXiv:1603.05279 [cs.CV].
  48. ↑ Khari Johnson (May 23, 2018). "Intel unveils Nervana Neural Net L-1000 for accelerated AI training". VentureBeat. https://venturebeat.com/2018/05/23/intel-unveils-nervana-neural-net-l-1000-for-accelerated-ai-training/. "...Intel will be extending bfloat16 support across our AI product lines, including Intel Xeon processors and Intel FPGAs." 
  49. ↑ Michael Feldman (May 23, 2018). "Intel Lays Out New Roadmap for AI Portfolio". TOP500 Supercomputer Sites. https://www.top500.org/news/intel-lays-out-new-roadmap-for-ai-portfolio/. "Intel plans to support this format across all their AI products, including the Xeon and FPGA lines" 
  50. ↑ Lucian Armasu (May 23, 2018). "Intel To Launch Spring Crest, Its First Neural Network Processor, In 2019". Tom's Hardware. https://www.tomshardware.com/news/intel-neural-network-processor-lake-crest,37105.html. "Intel said that the NNP-L1000 would also support bfloat16, a numerical format that's being adopted by all the ML industry players for neural networks. The company will also support bfloat16 in its FPGAs, Xeons, and other ML products. The Nervana NNP-L1000 is scheduled for release in 2019." 
  51. ↑ "Available TensorFlow Ops | Cloud TPU | Google Cloud". Google Cloud. https://cloud.google.com/tpu/docs/tensorflow-ops. "This page lists the TensorFlow Python APIs and graph operators available on Cloud TPU." 
  52. ↑ Elmar Haußmann (April 26, 2018). "Comparing Google's TPUv2 against Nvidia's V100 on ResNet-50". RiseML Blog. https://blog.riseml.com/comparing-google-tpuv2-against-nvidia-v100-on-resnet-50-c2bbb6a51e5e. "For the Cloud TPU, Google recommended we use the bfloat16 implementation from the official TPU repository with TensorFlow 1.7.0. Both the TPU and GPU implementations make use of mixed-precision computation on the respective architecture and store most tensors with half-precision." 
  53. ↑ Tensorflow Authors (February 28, 2018). "ResNet-50 using BFloat16 on TPU". Google. https://github.com/tensorflow/tpu/blob/master/benchmarks/ResNet-50_v1.5_Performance_Comparison_TensorFlow_1.12_GCP.md. [yes|permanent dead link|dead link}}]
  54. ↑ Joshua V. Dillon; Ian Langmore; Dustin Tran; Eugene Brevdo; Srinivas Vasudevan; Dave Moore; Brian Patton; Alex Alemi et al. (November 28, 2017). TensorFlow Distributions (Report). Accessed May 23, 2018. "All operations in TensorFlow Distributions are numerically stable across half, single, and double floating-point precisions (as TensorFlow dtypes: tf.bfloat16 (truncated floating point), tf.float16, tf.float32, tf.float64). Class constructors have a validate_args flag for numerical asserts" 
  55. ↑ "Google Reveals a Powerful New AI Chip and Supercomputer" (in en). https://www.technologyreview.com/2017/05/17/151656/google-reveals-a-powerful-new-ai-chip-and-supercomputer/. 
  56. ↑ "What to Expect From Apple's Neural Engine in the A11 Bionic SoC – ExtremeTech". https://www.extremetech.com/mobile/255780-apple-neural-engine-a11-bionic-soc. 
  57. ↑ "Facebook has a new job posting calling for chip designers". April 19, 2018. https://social.techcrunch.com/2018/04/18/facebook-has-a-new-job-posting-calling-for-chip-designers/. [yes|permanent dead link|dead link}}]
  58. ↑ "Facebook joins Amazon and Google in AI chip race". Financial Times. February 18, 2019. https://www.ft.com/content/1c2aab18-3337-11e9-bd3a-8b2a211d90d5. 
  59. ↑ Amadeo, Ron (May 11, 2021). "Samsung and AMD will reportedly take on Apple's M1 SoC later this year" (in en-us). https://arstechnica.com/gadgets/2021/05/report-the-samsung-amd-exynos-soc-will-be-out-for-laptops-this-year/. 
  60. ↑ Smith, Ryan. "The AI Race Expands: Qualcomm Reveals "Cloud AI 100" Family of Datacenter AI Inference Accelerators for 2020". https://www.anandtech.com/show/14187/qualcomm-reveals-cloud-ai-100-family-of-datacenter-ai-inference-accelerators-for-2020. 
  61. ↑ Woodie, Alex (2021-11-01). "Cerebras Hits the Accelerator for Deep Learning Workloads". https://www.datanami.com/2021/11/01/cerebras-hits-the-accelerator-for-deep-learning-workloads/. 
  62. ↑ "Cerebras launches new AI supercomputing processor with 2.6 trillion transistors" (in en-US). 2021-04-20. https://venturebeat.com/2021/04/20/cerebras-systems-launches-new-ai-supercomputing-processor-with-2-6-trillion-transistors/. 
  63. ↑ Abu Sebastian; Tomas Tuma; Nikolaos Papandreou; Manuel Le Gallo; Lukas Kull; Thomas Parnell; Evangelos Eleftheriou (2017). "Temporal correlation detection using computational phase-change memory". Nature Communications 8 (1): 1115. doi:10.1038/s41467-017-01481-9. PMID 29062022. Bibcode: 2017NatCo...8.1115S. 
  64. ↑ "A new brain-inspired architecture could improve how computers handle data and advance AI". American Institute of Physics. October 3, 2018. https://phys.org/news/2018-10-brain-inspired-architecture-advance-ai.html. 
  65. ↑ Carlos Ríos; Nathan Youngblood; Zengguang Cheng; Manuel Le Gallo; Wolfram H.P. Pernice; C. David Wright; Abu Sebastian; Harish Bhaskaran (2018). "In-memory computing on a photonic platform". Science Advances 5 (2): eaau5759. doi:10.1126/sciadv.aau5759. PMID 30793028. Bibcode: 2019SciA....5.5759R. 
  66. ↑ Zhong Sun; Giacomo Pedretti; Elia Ambrosi; Alessandro Bricalli; Wei Wang; Daniele Ielmini (2019). "Solving matrix equations in one step with cross-point resistive arrays". Proceedings of the National Academy of Sciences 116 (10): 4123–4128. doi:10.1073/pnas.1815682116. PMID 30782810. Bibcode: 2019PNAS..116.4123S. 
  67. ↑ 67.0 67.1 Marega, Guilherme Migliato; Zhao, Yanfei; Avsar, Ahmet; Wang, Zhenyu; Tripati, Mukesh; Radenovic, Aleksandra; Kis, Anras (2020). "Logic-in-memory based on an atomically thin semiconductor". Nature 587 (2): 72–77. doi:10.1038/s41586-020-2861-0. PMID 33149289. Bibcode: 2020Natur.587...72M. 
  68. ↑ 68.0 68.1 68.2 Feldmann, J.; Youngblood, N.; Karpov, M. et al. (2021). "Parallel convolutional processing using an integrated photonic tensor". Nature 589 (2): 52–58. doi:10.1038/s41586-020-03070-1. PMID 33408373. 
  69. ↑ "NVIDIA launches the World's First Graphics Processing Unit, the GeForce 256". http://www.nvidia.com/object/IO_20020111_5424.html. 
  70. ↑ "Intel to Bring a 'VPU' Processor Unit to 14th Gen Meteor Lake Chips". https://www.pcmag.com/news/intel-to-bring-a-vpu-processor-unit-to-14th-gen-meteor-lake-chips. 
  71. ↑ 71.0 71.1 71.2 Chen, Yu-Hsin; Emer, Joel; Sze, Vivienne (2017). "Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks". IEEE Micro: 1. doi:10.1109/mm.2017.265085944. ISSN 0272-1732. 
  72. ↑ 72.0 72.1 Han, Song; Liu, Xingyu; Mao, Huizi; Pu, Jing; Pedram, Ardavan; Horowitz, Mark A.; Dally, William J. (2016-02-03). EIE: Efficient Inference Engine on Compressed Deep Neural Network. OCLC 1106232247. 
  73. ↑ Reagen, Brandon; Whatmough, Paul; Adolf, Robert; Rama, Saketh; Lee, Hyunkwang; Lee, Sae Kyu; Hernandez-Lobato, Jose Miguel; Wei, Gu-Yeon et al. (June 2016). "Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators". 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA). Seoul: IEEE. pp. 267–278. doi:10.1109/ISCA.2016.32. ISBN 978-1-4673-8947-1. 
  74. ↑ Judd, Patrick; Albericio, Jorge; Moshovos, Andreas (2017-01-01). "Stripes: Bit-Serial Deep Neural Network Computing". IEEE Computer Architecture Letters 16 (1): 80–83. doi:10.1109/lca.2016.2597140. ISSN 1556-6056. 
  75. ↑ 75.0 75.1 75.2 "In-Datacenter Performance Analysis of a Tensor Processing Unit". Association for Computing Machinery. 24 June 2017. pp. 1-12. doi:10.1145/3079856.3080246. https://dl.acm.org/doi/10.1145/3079856.3080246. 
  76. ↑ "MLU 100 intelligence accelerator card". Cambricon. 2024. https://www.cambricon.com/index.php?m=content&c=index&a=lists&catid=21. 
  77. ↑ 77.0 77.1 Chi, Ping; Li, Shuangchen; Xu, Cong; Zhang, Tao; Zhao, Jishen; Liu, Yongpan; Wang, Yu; Xie, Yuan (June 2016). "PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory". 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA). IEEE. pp. 27–39. doi:10.1109/isca.2016.13. ISBN 978-1-4673-8947-1. 
  78. ↑ 78.0 78.1 78.2 Song, Linghao; Qian, Xuehai; Li, Hai; Chen, Yiran (February 2017). "PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning". 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE. pp. 541–552. doi:10.1109/hpca.2017.55. ISBN 978-1-5090-4985-1. 
  79. ↑ Shin, Dongjoo; Lee, Jinmook; Lee, Jinsu; Yoo, Hoi-Jun (2017). "14.2 DNPU: An 8.1TOPS/W reconfigurable CNN-RNN processor for general-purpose deep neural networks". 2017 IEEE International Solid-State Circuits Conference (ISSCC). pp. 240–241. doi:10.1109/ISSCC.2017.7870350. ISBN 978-1-5090-3758-2. https://ieeexplore.ieee.org/document/7870350. Retrieved 2023-08-24. 
  80. ↑ Lee, Jinmook; Kim, Changhyeon; Kang, Sanghoon; Shin, Dongjoo; Kim, Sangyeob; Yoo, Hoi-Jun (2018). "UNPU: A 50.6TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision". 2018 IEEE International Solid - State Circuits Conference - (ISSCC). pp. 218–220. doi:10.1109/ISSCC.2018.8310262. ISBN 978-1-5090-4940-0. https://ieeexplore.ieee.org/document/8310262. Retrieved 2023-11-30. 
  81. ↑ Liu, Shaoli; Du, Zidong; Tao, Jinhua; Han, Dong; Luo, Tao; Xie, Yuan; Chen, Yunji; Chen, Tianshi (June 2016). "Cambricon: An Instruction Set Architecture for Neural Networks". 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA). IEEE. pp. 393–405. doi:10.1109/isca.2016.42. ISBN 978-1-4673-8947-1. 
  82. ↑ 82.0 82.1 Ambrogio, Stefano; Narayanan, Pritish; Tsai, Hsinyu; Shelby, Robert M.; Boybat, Irem; di Nolfo, Carmelo; Sidler, Severin; Giordano, Massimo et al. (June 2018). "Equivalent-accuracy accelerated neural-network training using analogue memory". Nature 558 (7708): 60–67. doi:10.1038/s41586-018-0180-5. ISSN 0028-0836. PMID 29875487. Bibcode: 2018Natur.558...60A. 
  83. ↑ Chen, Wei-Hao; Lin, Wen-Jang; Lai, Li-Ya; Li, Shuangchen; Hsu, Chien-Hua; Lin, Huan-Ting; Lee, Heng-Yuan; Su, Jian-Wei et al. (December 2017). "A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme". 2017 IEEE International Electron Devices Meeting (IEDM). IEEE. pp. 28.2.1–28.2.4. doi:10.1109/iedm.2017.8268468. ISBN 978-1-5386-3559-9. 
  84. ↑ Yang, J. Joshua; Strukov, Dmitri B.; Stewart, Duncan R. (January 2013). "Memristive devices for computing" (in en). Nature Nanotechnology 8 (1): 13–24. doi:10.1038/nnano.2012.240. ISSN 1748-3395. PMID 23269430. Bibcode: 2013NatNa...8...13Y. https://www.nature.com/articles/nnano.2012.240. 
  85. ↑ Shafiee, Ali; Nag, Anirban; Muralimanohar, Naveen; Balasubramonian, Rajeev; Strachan, John Paul; Hu, Miao; Williams, R. Stanley; Srikumar, Vivek (2016-10-12). "ISAAC". ACM SIGARCH Computer Architecture News 44 (3): 14–26. doi:10.1145/3007787.3001139. ISSN 0163-5964. 
  86. ↑ Ji, Yu Zhang, Youyang Xie, Xinfeng Li, Shuangchen Wang, Peiqi Hu, Xing Zhang, Youhui Xie, Yuan (2019-01-27). FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture. OCLC 1106329050. 
  87. ↑ Nandakumar, S. R.; Boybat, Irem; Joshi, Vinay; Piveteau, Christophe; Le Gallo, Manuel; Rajendran, Bipin; Sebastian, Abu; Eleftheriou, Evangelos (November 2019). "Phase-Change Memory Models for Deep Learning Training and Inference". 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS). IEEE. pp. 727–730. doi:10.1109/icecs46596.2019.8964852. ISBN 978-1-7281-0996-1. 
  88. ↑ Joshi, Vinay; Le Gallo, Manuel; Haefeli, Simon; Boybat, Irem; Nandakumar, S. R.; Piveteau, Christophe; Dazzi, Martino; Rajendran, Bipin et al. (2020-05-18). "Accurate deep neural network inference using computational phase-change memory". Nature Communications 11 (1): 2473. doi:10.1038/s41467-020-16108-9. ISSN 2041-1723. PMID 32424184. Bibcode: 2020NatCo..11.2473J. 
  89. ↑ "Nvidia claims 'record performance' for Hopper MLPerf debut". https://www.theregister.com/2022/09/09/nvidia_hopper_mlperf/. 
  90. ↑ "Development of a machine vision system for weed control using precision chemical application". http://www.abe.ufl.edu/wlee/Publications/ICAME96.pdf. 
  91. ↑ "Self-Driving Cars Technology & Solutions from NVIDIA Automotive". https://www.nvidia.com/en-us/self-driving-cars/. 
  92. ↑ "movidius powers worlds most intelligent drone". March 16, 2016. https://www.siliconrepublic.com/machines/movidius-dji-drone. 
  93. ↑ "Qualcomm Research brings server class machine learning to everyday devices–making them smarter [VIDEO"]. October 2015. https://www.qualcomm.com/news/onq/2015/10/01/qualcomm-research-brings-server-class-machine-learning-everyday-devices-making. 

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