Engineering:ARM Cortex-X1
| General Info | |
|---|---|
| Launched | 2020 |
| Designed by | ARM Ltd. |
| Performance | |
| Max. CPU clock rate | to 3.0 GHz in phones and 3.3 GHz in tablets/laptops |
| Address width | 40-bit |
| Cache | |
| L1 cache | 128 KiB (64 KiB I-cache with parity, 64 KiB D-cache) per core |
| L2 cache | 512–1024 KiB per core |
| L3 cache | 512 KiB – 8 MiB (optional) |
| Architecture and classification | |
| Architecture | ARMv8-A |
| Microarchitecture | ARM Cortex-X1 |
| Instruction set | A64, A32, and T32 (at the EL0 only) |
| Extensions |
|
| Physical specifications | |
| Cores |
|
| Products, models, variants | |
| Product code name(s) |
|
| Variant(s) | ARM Cortex-A78 |
| History | |
| Predecessor | ARM Cortex-A77 |
| Successor | ARM Cortex-X2 |
The ARM Cortex-X1 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin, Texas design centre as part of ARM's Cortex-X Custom (CXC) program.[1][2]
Design
The Cortex-X1 design is based on the ARM Cortex-A78, but redesigned for purely performance instead of a balance of performance, power, and area (PPA).[1]
The Cortex-X1 is a 5-wide decode out-of-order superscalar design with a 3K macro-OP (MOPs) cache. It can fetch 5 instructions and 8 MOPs per cycle, and rename and dispatch 8 MOPs, and 16 µOPs per cycle. The out-of-order window size has been increased to 224 entries. The backend has 15 execution ports with a pipeline depth of 13 stages and the execution latencies consists of 10 stages. It also features 4x128b SIMD units.[3][4][5][6]
ARM claims the Cortex-X1 offers 30% faster integer and 100% faster machine learning performance than the ARM Cortex-A77.[3][4][5][6]
The Cortex-X1 supports ARM's DynamIQ technology, expected to be used as high-performance cores when used in combination with the ARM Cortex-A78 mid and ARM Cortex-A55 little cores.[1][2]
Architecture changes in comparison with ARM Cortex-A78
- Around 20% performance improvement (+30% from A77)[7]
- 30% faster integer
- 100% faster machine learning performance
- Out-of-order window size has been increased to 224 entries (from 160 entries)
- Up to 4x128b SIMD units (from 2x128b)
- 15% more silicon area
- 5-way decode (from 4-way)
- 8 MOPs/cycle decoded cache bandwidth (from 6 MOPs/cycle)
- 64 KB L1D + 64 KB L1I (from 32/64 KB L1)
- Up to 1 MB/core L2 cache (from 512 KB/core max)
- Up to 8 MB L3 cache (from 4 MB max)
Licensing
The Cortex-X1 is available as SIP core to partners of their Cortex-X Custom (CXC) program, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).[1][2]
Usage
- Samsung Exynos 2100[8]
- Qualcomm Snapdragon 888(+)[9]
- Google Tensor[10]
See also
- ARM Cortex-A78, related high performance microarchitecture
- Comparison of ARMv8-A cores, ARMv8 family
References
- ↑ 1.0 1.1 1.2 1.3 "Introducing the Arm Cortex-X Custom program" (in en). https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-cortex-x-custom-program.
- ↑ 2.0 2.1 2.2 Ltd, Arm. "Cortex-X Custom CPU program" (in en). https://www.arm.com/products/cortex-x.
- ↑ 3.0 3.1 Frumusanu, Andrei. "Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence". https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging.
- ↑ 4.0 4.1 "Arm Cortex-X1: The First From The Cortex-X Custom Program" (in en-US). 2020-05-26. https://fuse.wikichip.org/news/3543/arm-cortex-x1-the-first-from-the-cortex-x-custom-program/.
- ↑ 5.0 5.1 McGregor, Jim. "Arm Unleashes CPU Performance With Cortex-X1" (in en). https://www.forbes.com/sites/tiriasresearch/2020/05/26/arm-unleashes-cpu-performance-with-cortex-x1/.
- ↑ 6.0 6.1 "Arm Cortex-X1 and Cortex-A78 CPUs: Big cores with big differences" (in en-US). 2020-05-26. https://www.androidauthority.com/arm-cortex-x1-cortex-a78-1119666/.
- ↑ "Cortex-X1 - Microarchitectures - ARM - WikiChip" (in en). https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-x1.
- ↑ "Exynos 2100 5G Mobile Processor: Specs, Features | Samsung" (in en). https://www.samsung.com/semiconductor/minisite/exynos/products/mobileprocessor/exynos-2100/.
- ↑ "Qualcomm Snapdragon 888 5G Mobile Platform | Latest 5G Snapdragon Processor | Qualcomm". https://www.qualcomm.com/products/snapdragon-888-5g-mobile-platform.
- ↑ Amadeo, Ron (2021-10-19). "The “Google Silicon” team gives us a tour of the Pixel 6’s Tensor SoC". https://arstechnica.com/gadgets/2021/10/the-google-silicon-team-gives-us-a-tour-of-the-pixel-6s-tensor-soc/.
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