Engineering:ARM Cortex-X2

Short description: Microprocessor core model by ARM

ARM Cortex-X2

General Info
Launched	2021
Designed by	ARM Ltd.
Performance
Max. CPU clock rate	2.84 GHz  to 3.92 GHz
Cache
L1 cache	128 KiB (64 KiB I-cache with parity, 64 KiB D-cache) per core
L2 cache	512–1024 KiB per core
L3 cache	512 KiB – 8 MiB (optional)
Architecture and classification
Architecture	ARMv9-A
Microarchitecture	ARM Cortex-X2
Products, models, variants
Product code name(s)	Matterhorn ELP
Variant(s)	ARM Cortex-A710
History
Predecessor	ARM Cortex-X1
Successor	ARM Cortex-X3

The ARM Cortex-X2 is a microarchitecture implementing the ARMv9-A 64-bit instruction set designed by ARM Holdings' Austin, Texas design centre as part of ARM's Cortex-X Custom (CXC) program.

Architecture changes in comparison with ARM Cortex-X1

The processor implements the following changes:

• 10 cycle pipeline down from 11, created by reducing the dispatch stage from 2 cycles to 1
• reorder buffer increased by 30% from 224 entries to 288
• dTLB increased by 20% from 40 entries to 48
• SVE2 SIMD support
• Bfloat16 data type support
• Support for Aarch32 removed
• Comparing the Cortex-X2 with 8MB of L3 cache to the Cortex-X1 with 4MB of L3 cache:
  • 16% greater integer performance
  • 100% greater ML performance

Usage

• MediaTek Dimensity 9000/9000+
• Qualcomm Snapdragon 8/8+ Gen 1
• Samsung Exynos 2200

See also

• ARM Cortex-A710, related high performance microarchitecture