Execute instruction

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Short description: Computer instruction executing another instruction

In a computer instruction set architecture (ISA), an execute instruction is a machine language instruction which treats data as a machine instruction and executes it.

It can be considered a fourth mode of instruction sequencing after ordinary sequential execution, branching, and interrupting.[1] Since it is an instruction that operates on other instructions like the repeat instruction, it has also been classified as a meta-instruction.[2]

Computer models

Many computer families introduced in the 1950s and 1960s include execute instructions: the IBM 709[1] and IBM 7090 (op code mnemonic: XEC),[3] the IBM 7030 Stretch (EX, EXIC),[4][1] the PDP-1/-4/-7/-9/-15 (XCT),[5][6] the UNIVAC 1100/2200 (EXRI),[7] the CDC 924 (XEC),[8] the PDP-6/-10 (XCT), the IBM System/360 (EX),[9] the GE-600/Honeywell 6000 (XEC, XED),[10] the SDS-9xx (EXU),[11] the SDS 92 (EXU),[12] and the SDS Sigma series (EXU).[13]

Fewer 1970s designs include execute instructions: the Nuclear Data 812 minicomputer (1971) (XCT),[14] the HP 3000 (1972) (XEQ),[15] and the Texas Instruments TI-990 (1975)[16] and its microprocessor version, the TMS9900 (1976) (X).[17] An execute instruction was proposed for the PDP-11 in 1970,[18] but never implemented for it[19] or its successor, the VAX.[20]

Modern instruction sets do not include execute instructions because they interfere with pipelining, prefetching, and other optimizations.[citation needed]

Semantics

The instruction to be executed, the target instruction, may be in a register or fetched from memory. Some architectures allow the target instruction to itself be an execute instruction; others do not.

The target instruction is executed as if it were in the memory location of the execute instruction. If, for example, it is a subroutine call instruction, execution is transferred to the subroutine, with the return location being the location after the execute instruction. However, some architectures implement variants of the execute instruction which inhibit branches.[1]

The System/360 supports variable-length target instructions. It also supports modifying the target instruction before executing it. The target instruction must start on an even-numbered byte.[9]

The GE-600 series supports execution of two-instruction sequences, which must be doubleword-aligned.[10]

Some architectures support an execute instruction which operates in a different protection and address relocation mode. For example, the ITS PDP-10 paging device supports a privileged-mode XCTR 'execute relocated' instruction which allows memory reads, writes, or both to use the user-mode page mappings.[21] Similarly, the KL10 variant of the PDP-10 supports the privileged instruction PXCT 'previous context XCT'.[22]

The execute instruction can cause several problems when one execute instruction points to another one and so on:

  • the processor may be uninterruptible for multiple clock cycles if the execute instruction cannot be interrupted in the middle of execution;
  • similarly, the processor may go into an infinite loop if the series of execute instructions is circular and uninterruptible;
  • if the execute instructions are on different swap pages, all of the pages need to be swapped in for the instruction to complete, which can cause thrashing.

Similar issues arise with multilevel indirect addressing modes.

Applications

The execute instruction has several applications:[1]

  • Functioning as a single-instruction subroutine without the usual overhead of subroutine calls; that instruction may call a full subroutine if necessary.[1]
  • Late binding
    • Implementation of call by name and other thunks.[1]
    • A table of execute targets may be used for dynamic dispatch of the methods or virtual functions of an object or class, especially when the method or function may often be implementable as a single instruction.[19]
    • An execute target may contain a hook for adding functionality or for debugging; it is normally initialized as a NOP which may be overridden dynamically.
    • An execute target may change between a fast version of an operation and a fully traced version.[23][24][25]
  • Tracing, monitoring, and emulation
    • This may maintain a pseudo-program counter, leaving the normal program counter unchanged.[1]
  • Executing dynamically generated code, especially when memory protection prevents executable code from being writable.
  • Emulating self-modifying code, especially when it must be reentrant or read-only.[18]
  • In the IBM System/360, the execute instruction can modify bits 8-15 of the target instruction, effectively turning an instruction with a fixed argument (e.g., a length field) into an instruction with a variable argument.
  • Privileged-mode execute instructions as on the KL10 are used by operating system kernels to execute operations such as block copies within the virtual space of user processes.

Notes

  1. ↑ 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Brooks, F.P. (March 1960). "The execute operations—a fourth mode of instruction sequencing". Communications of the ACM 3 (3): 168–170. doi:10.1145/367149.367168. 
  2. ↑ Rossman, George E. (December 1975). "A Course of Study in Computer Hardware Architecture". IEEE Computer 8 (12): 44–63. doi:10.1109/C-M.1975.218835. , p. 50
  3. ↑ Reference Manual, IBM 7090 Data Processing System. IBM. March 1962. p. 36. http://www.bitsavers.org/pdf/ibm/7090/22-6528-4_7090Manual.pdf. 
  4. ↑ Reference Manual, 7030 Data Processing System. IBM. August 1961. p. 50. http://bitsavers.org/pdf/ibm/7030/22-6530-2_7030RefMan.pdf. 
  5. ↑ Programmed Data Processor-1 Manual. Digital Equipment Corporation. 1961. p. 14. http://gordonbell.azurewebsites.net/digital/pdp%201%20manual%201961.pdf. 
  6. ↑ Supnik, Bob. "Architectural Evolution in DEC's 18b Computers". p. 8 (page numbers not shown). http://simh.trailing-edge.com/docs/architecture18b.pdf. 
  7. ↑ Univac 1107 Central Computer. November 1961. p. 12-1. http://www.bitsavers.org/pdf/univac/1107/UT-2463_CPU_Nov61.pdf. 
  8. ↑ Control Data 924 Computer Reference Manual. October 1962. p. 2-41. http://bitsavers.informatik.uni-stuttgart.de/pdf/cdc/924/168B_CDC_924_Reference_Manual_Oct62.pdf. 
  9. ↑ 9.0 9.1 IBM System/360 Principles of Operation. IBM. 1964. p. 65. A22-6821-0. http://bitsavers.trailing-edge.com/pdf/ibm/360/princOps/A22-6821-0_360PrincOps.pdf. 
  10. ↑ 10.0 10.1 GE-635 System Manual. General Electric Computer Department. July 1964. p. A-5. http://www.bitsavers.org/pdf/ge/GE-6xx/CPB-371A_GE-635_System_Man_196407.pdf. 
  11. ↑ SDS 940 Theory of Operation. Scientific Data Systems. March 1967. p. 2-12. SDS-98-01-26A. https://doc.lagout.org/science/0_Computer%20Science/0_Computer%20History/old-hardware/sds/9xx/940/980126A_940_TheoryOfOperation_Mar67.pdf. 
  12. ↑ SDS 92 Computer. Scientific Data Systems. June 1965. p. 2-6. https://usermanual.wiki/Document/900505CSDS92ReferenceJun65.3199204510/view. 
  13. ↑ Xerox SIGMA 7 Computer: Reference Manual. 90 09 5J; XG46, File No: 1X03 (0 ed.). Xerox Corporation. October 1973. pp. 70–71. http://www.bitsavers.org/pdf/sds/sigma/sigma7/900950J_Sigma7_RefMan_Oct73.pdf. 
  14. ↑ Principles of Programming the ND812 Computer. Nuclear Data, Inc.. 1971. p. 4-4. http://bitsavers.trailing-edge.com/pdf/nd/ND812/ND812_Prog.pdf. 
  15. ↑ HP 3000 Computer System: Machine Instruction Set Reference Manual. Hewlett-Packard. 1980. p. 2-31. http://www.bitsavers.org/pdf/hp/3000/instrSet/30000-90022_InsSetRef_Feb80.pdf. 
  16. ↑ 990 Computer Family Systems Handbook. Texas Instruments. p. 3-28. http://www.bitsavers.org/pdf/ti/990/945250-9701_990_Computer_Family_Systems_Handbook_3ed_May76.pdf. 
  17. ↑ TMS 9900 Microprocessor Data Manual. Texas Instruments. December 1976. p. 24. http://datasheets.chipdb.org/TI/9900/TMS9900_DataManual.pdf. 
  18. ↑ 18.0 18.1 van de Goor, Ad (September 21, 1970). "The Execute Instruction". http://bitsavers.informatik.uni-stuttgart.de/pdf/dec/pdp11/memos/700921_The_Execute_Instruction.pdf. 
  19. ↑ 19.0 19.1 PDP11 Processor Handbook: PDP11/04/34a/44/60/60. Digital Equipment Corporation. 1979. http://bitsavers.org/pdf/dec/pdp11/handbooks/PDP11_Handbook1979.pdf. 
  20. ↑ VAX MACRO and Instruction Set Reference Manual. Compaq Computer Corporation. April 2001. AA-PS6GD-TE. https://www.ece.lsu.edu/ee4720/doc/vax.pdf. 
  21. ↑ Holloway, J. (February 20, 1970). "Hardware Memo 2 - PDP-10 Paging Device". MIT AI Lab. p. 11. http://www.bitsavers.org/pdf/mit/ai/ai_600dpi/HW_Memo_2_PDP-10_Paging_Device_Feb1970.pdf. 
  22. ↑ DECsystem-10, DECSYSTEM-20 Processor Reference Manual. Digital Equipment Corporation. June 1982. p. 2-63. AA-H391A-TK, AD-H391A-T1. https://www.livingcomputers.org/UI/UserDocs/Tops-10-v7-04/3_DECsystem-10_DECSYSTEM-20_Processor_Reference.pdf. 
  23. ↑ Gabriel, Richard P. (August 1985). Performance and Evaluation of Lisp Systems. MIT Press. p. 32. ISBN 9780262070935. https://www.dreamsongs.com/Files/Timrep.pdf. 
  24. ↑ Pitman, Kent M.. The Revised Maclisp Manual, Sunday Morning Edition. https://www.maclisp.info/pitmanual/. 
  25. ↑ Moon, David A. (April 1974). Maclisp Reference Manual. p. 181. http://www.softwarepreservation.com/projects/LISP/MIT/Moon-MACLISP_Reference_Manual-Apr_08_1974.pdf. 



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