Software:coreboot

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Short description: Open-source computer firmware

coreboot
Graphic of a running hare in black and white above text "coreboot" in lowercase sans-serif font
Original author(s)Ronald G. Minnich, Eric Biederman, Li-Ta (Ollie) Lo, Stefan Reinauer, and the coreboot community
Initial release1999; 25 years ago (1999)
Stable release
4.20.1 / 3 June 2023; 13 months ago (2023-06-03)[1]
Written inMostly C, about 1% in assembly and optionally SPARK
PlatformIA-32, x86-64, ARMv7,[2] ARMv8, MIPS, RISC-V, POWER8
TypeFirmware
LicenseGPLv2[3]

coreboot, formerly known as LinuxBIOS,[4] is a software project aimed at replacing proprietary firmware (BIOS or UEFI) found in most computers with a lightweight firmware designed to perform only the minimum number of tasks necessary to load and run a modern 32-bit or 64-bit operating system.

Since coreboot initializes the bare hardware, it must be ported to every chipset and motherboard that it supports. As a result, coreboot is available only for a limited number of hardware platforms and motherboard models.

One of the coreboot variants is Libreboot, a software distribution partly free of proprietary blobs, aimed at end users.

History

The coreboot project began with the goal of creating a BIOS that would start fast and handle errors intelligently.[5] It is licensed under the terms of the GNU General Public License version 2 (GPLv2). Main contributors include LANL, SiS, AMD, Coresystems and Linux Networx, Inc, as well as motherboard vendors MSI, Gigabyte and Tyan, which offer coreboot alongside their standard BIOS or provide specifications of the hardware interfaces for some of their motherboards. Google partly sponsors the coreboot project.[6] CME Group, a cluster of futures exchanges, began supporting the coreboot project in 2009.[7]

Other than the first three models, all Chromebooks run coreboot.[8] Code from Das U-Boot has been assimilated to enable support for processors based on the ARM instruction set.[9]

In June 2019, coreboot began to use the NSA software Ghidra for its reverse engineering efforts on firmware-specific problems following the release of the suite as free and open source software.[10]

Supported platforms

CPU architectures supported by coreboot include IA-32, x86-64, ARM, ARM64, MIPS and RISC-V. Supported system-on-a-chip (SOC) platforms include AMD Geode, starting with the Geode GX processor developed for the OLPC. Artec Group added Geode LX support for its ThinCan model DBE61; that code was adopted by AMD and further improved for the OLPC after it was upgraded to the Geode LX platform, and is further developed by the coreboot community to support other Geode variants. coreboot can be flashed onto a Geode platform using Flashrom.

From that initial development on AMD Geode based platforms, coreboot support has been extended onto many AMD processors and chipsets. The processor list includes Family 0Fh and 10h (K8 core), and recently Family 14h (Bobcat core, Fusion APU). coreboot support also extends to AMD chipsets: RS690, RS7xx, SB600, and SB8xx.

In AMD Generic Encapsulated Software Architecture (AGESA)‍—‌a bootstrap protocol by which system devices on AMD64 mainboards are initialized‍—‌was open sourced in early 2011, aiming to provide required functionality for coreboot system initialization on AMD64 hardware.[11] However, as of 2014 such releases never became the basis for future development by AMD, and were subsequently halted.[12]

Devices that could be preloaded with coreboot or one of its derivatives include:

Lenovo/IBM
The Libreboot T400 and X200 (rebranded ThinkPad T400 and X200, respectively, available from Minifree, previously known as Gluglug).[13][14]
Artec Group
ThinCan models DBE61, DBE62 and DBE63, and fanless server/router hardware manufactured by PC Engines.[15]
Purism
Librem laptops come with coreboot.[16][17]
Others
Some System76 PCs use coreboot TianoCore firmware, including open source Embedded Controller firmware.
Dasharo offers an alternative coreboot-based firmware distribution for computers from MSI, NovaCustom and Nitrokey, among others.[18][19][20]
StarLabs Systems use coreboot firmware, as an alternative.[21]

Design

coreboot typically loads a Linux kernel, but it can load any other stand-alone ELF executable, such as iPXE, gPXE or Etherboot that can boot a Linux kernel over a network, or SeaBIOS[22] that can load a Linux kernel, Windows 2000 and later, and BSDs; Windows 2000/XP and OpenBSD support was previously provided by ADLO.[23][24] coreboot can also load a kernel from any supported device, such as Myrinet, Quadrics, or SCI cluster interconnects. Booting other kernels directly is also possible, such as a Plan 9 kernel. Instead of loading a kernel directly, coreboot can pass control to a dedicated boot loader, such as a coreboot-capable version of GNU GRUB 2.

coreboot is written primarily in C, with a small amount of assembly code. Choosing C as the primary programming language enables easier code audits when compared to contemporary PC BIOS that was generally written in assembly,[25] which results in improved security. There is build and runtime support to write parts of coreboot in Ada[26] to further raise the security bar, but it is currently only sporadically used. The source code is released under the GNU GPL version 2 license.

coreboot performs the absolute minimal amount of hardware initialization and then passes control to the operating system. As a result, there is no coreboot code running once the operating system has taken control. A feature of coreboot is that the x86 version runs in 32-bit mode after executing only ten instructions[27] (almost all other x86 BIOSes run exclusively in 16-bit mode). This is similar to the modern UEFI firmware, which is used on newer PC hardware.

Initializing DRAM

The most difficult hardware that coreboot initializes is the DRAM controllers and DRAM. In some cases, technical documentation on this subject is NDA restricted or unavailable. RAM initialization is particularly difficult because before the RAM is initialized it cannot be used. Therefore, to initialize DRAM controllers and DRAM, the initialization code may have only the CPU's general purpose registers or Cache-as-RAM as temporary storage.

romcc, a C compiler that uses registers instead of RAM, eases the task. Using romcc, it is relatively easy to make SMBus accesses to the SPD ROMs of the DRAM DIMMs, that allows the RAM to be used.

With newer x86 processors, the processor cache can be used as RAM until DRAM is initialized. The processor cache has to be initialized into Cache-as-RAM[28][29] mode as well, but this needs fewer instructions than initializing DRAM. Also, the Cache-as-RAM mode initialization is specific to CPU architectures, thus more generic than DRAM initialization, which is specific to each chipset and mainboard.

For most modern x86 platforms, closed source binary-only components provided by the vendor are used for DRAM setup. For Intel systems, FSP-M is required, while AMD has no current support. Binary AGESA is currently used for proprietary UEFI firmware on AMD systems, and this model is expected to carry over to any future AMD-related coreboot support.[30]

Developing and debugging coreboot

Hacking coreboot at Denver 2008 summit.

There are also CPU emulators that either replace the CPU or connect via a JTAG port, with the Sage SmartProbe[31][32] being an example. Code can be built on, or downloaded to, BIOS emulators rather than flashing the BIOS device.

Payloads

SeaBIOS payload running on a Lenovo ThinkPad X60

coreboot can load a payload, which may be written using the libpayload helper library. Existing payloads include the following:

European Coreboot Conference

One physical meeting is the European Coreboot Conference which was organized in October 2017 and lasted for three days.

Conference history

Event and year Date Host city Venue Resources Themes
ECC2017 26.10. – 29.10 Bochum, Germany RUB Convention Center https://ecc2017.com

Variants

coreboot has a number of variants from its original code base each with slightly different objectives:.

  • Libreboot - A variant with a primary focus to remove some[35] binary blobs.
  • osboot - A variant similar to Libreboot that scrapped its only some blobs policy to increase hardware support and stability.[36] As of November 2022 merged with libreboot.[37]
  • MrChromebox has developed a modified version of coreboot for ChromeOS based devices.[38]
  • GNU Boot - A variant with a primary focus to remove all binary blobs.[39]
  • Canoeboot[40]

See also

References

  1. ↑ "Releases". n.d.. https://www.coreboot.org/releases. 
  2. ↑ "ARM". coreboot. 15 October 2013. https://www.coreboot.org/ARM. 
  3. ↑ "coreboot's licence". 1991. https://github.com/coreboot/coreboot/blob/master/COPYING. 
  4. ↑ "[LinuxBIOS] Welcome to coreboot". 12 January 2008. http://coreboot.org/pipermail/coreboot/2008-January/029135.html. 
  5. ↑ Anton Borisov: The Open Source BIOS is Ten. An interview with the coreboot developers . The H, 2009.
  6. ↑ "Google Sponsors the LinuxBIOS project". http://google-code-updates.blogspot.com/2006/11/google-sponsors-linuxbios-project.html. 
  7. ↑ "CME Group Dives Into Coreboot and Other Linux Open Source Projects". Wall Street & Technology. http://www.wallstreetandtech.com/it-infrastructure/showArticle.jhtml?articleID=217400294. 
  8. ↑ "Chromebooks". coreboot. 16 January 2014. http://www.coreboot.org/Chromebooks. 
  9. ↑ "GSoC2011(Week 1): Analysis of U-boot ARM boot code | coreboot developer blogs". 5 June 2011. http://blogs.coreboot.org/blog/2011/06/05/gsoc2011week-1-analysis-of-u-boot-arm-boot-code/. 
  10. ↑ "Coreboot nutzt NSA-Tool zum Reverse Engineering". https://www.golem.de/news/ghidra-coreboot-nutzt-nsa-tool-zum-reverse-engineering-1906-141746.html. 
  11. ↑ "Technical details on AMD's coreboot source code release". AMD. 28 February 2011. http://community.amd.com/community/amd-blogs/business/embedded-systems/blog/2011/02/28/technical-details-on-amd-s-coreboot-source-code-release. 
  12. ↑ Griffith, Bruce (2014-11-05). "AMD's binary-only AGESA libraries". https://mail.coreboot.org/pipermail/coreboot/2014-November/078892.html. 
  13. ↑ "Minifree". http://minifree.org/. 
  14. ↑ "The Gluglug". fsf.org. https://www.fsf.org/resources/hw/endorsement/gluglug. 
  15. ↑ "pcengines/coreboot". https://github.com/pcengines/coreboot. 
  16. ↑ "coreboot Firmware on Purism Librem devices". https://puri.sm/coreboot/. 
  17. ↑ "Purism Laptops To Use 'Heads' Firmware To Protect Against Rootkits, Tampering (Updated)". 27 February 2018. https://www.tomshardware.com/news/purism-heads-rootkit-tampering-protection,34128.html. 
  18. ↑ "New Dasharo v1.1 Firmware For The MSI Z690 Board - Phoronix". 22 November 2022. https://www.phoronix.com/news/Dasharo-1.1-MSI-Z690-Board. 
  19. ↑ "NovaCustom-Dasharo October-2023 Firmware Update (ADL v1.7.0 & TGL v1.5.0) - NovaCustom". 19 September 2023. https://configurelaptop.eu/novacustom-dasharo-october-2023-firmware-update-adl-v1-7-0-tgl-v1-5-0/. 
  20. ↑ "The NitroPC Pro is Qubes-Certified! - Nitrokey". 24 September 2023. https://www.nitrokey.com/news/2023/nitropc-pro-qubes-certified. 
  21. ↑ Starbook mk v review - fossbytes
  22. ↑ SeaBIOS (previously known as LegacyBIOS) is an open-source legacy BIOS implementation
  23. ↑ "coreboot Add-on Layer (ADLO)". Archived from the original on 25 November 2010. https://web.archive.org/web/20101125130605/http://www.coreboot.org/ADLO. 
  24. ↑ SEBOS, Security Enhanced Bootloader for Operating Systems, Phase 2 , adding PC BIOS Services to coreboot via Bochs BIOS (Link noted to be defunct on 18 July 2008. See )
  25. ↑ Comparison of UEFI and legacy BIOS, pronouncing that same advantage for UEFI
  26. ↑ commit adding that support
  27. ↑ "coreboot v3 early startup code". http://lxr.linux.no/coreboot-v3+r777/arch/x86/geodelx/stage0.S. 
  28. ↑ "CAR: Using Cache as RAM in Linux BIOS". qmqm.pl. 15 January 2009. http://rere.qmqm.pl/~mirq/cache_as_ram_lb_09142006.pdf. 
  29. ↑ "A Framework for Using Processor Cache as RAM (CAR)". http://www.coreboot.org/images/6/6c/LBCar.pdf. 
  30. ↑ Griffith, Bruce (5 November 2014). "[coreboot AMD's binary-only AGESA libraries"]. https://mail.coreboot.org/pipermail/coreboot/2014-November/078892.html. 
  31. ↑ "Sage Electronic Engineering - SmartProbe JTAG debugger, Sage EDK, coreboot and Embedded Systems and Software Engineering". Archived from the original on 15 March 2011. https://web.archive.org/web/20110315080000/http://www.se-eng.com/. 
  32. ↑ "Sage SmartProbe FAQ". S.Datskovskiy. http://www.loper-os.org/?p=1887. 
  33. ↑ "Depthcharge: The ChromeOS bootloader". https://docs.google.com/presentation/d/1pH8ltQ3cGKy9dRaTxHtZbA50QLZCw6HE8LDoi1y_gcs/pub?start=false&loop=false&delayms=3000#slide=id.p. 
  34. ↑ "Modify u-boot code to allow building coreboot payload. [chromiumos/third_party/u-boot-next : chromeos-v2011.03]". 24 July 2011. https://groups.google.com/a/chromium.org/group/chromium-os-reviews/browse_thread/thread/8daf5b5ffe245c1d/0eda7e414407a923. 
  35. ↑ "Binary Blob Reduction Policy". 2023-11-01. https://libreboot.org/news/policy.html. 
  36. ↑ "osboot project". 2021-03-15. https://osboot.org/. 
  37. ↑ "Libreboot – Osboot is now part of Libreboot". 2022-12-19. https://libreboot.org/news/merge.html. 
  38. ↑ "How to install ChromeOS Flex on a Chromebook" (in en). 2022-04-17. https://www.androidpolice.com/install-chromeos-flex-chromebook-explainer/. 
  39. ↑ "GNU Boot Summary". 2023-10-30. https://savannah.gnu.org/projects/gnuboot. 
  40. ↑ "Canoeboot project". 16 November 2023. https://canoeboot.org/. 

Further reading

External links



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