Advanced Programmable Interrupt Controller: Difference between revisions

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{{Short description|Family of computer interrupt controllers}}
{{Short description|Family of computer interrupt controllers}}
{{Infobox technology standard
| title            = Advanced Programmable Interrupt Controller
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| abbreviation      = APIC
| native_name      = <!-- Name in local language. If more than one, separate using {{plain list}} -->
| native_name_lang  = <!-- ISO 639-1 code e.g. "fr" for French. If more than one, use {{lang}} inside native_name items instead -->
| status            = Active
| year_started      = <!-- {{Start date|YYYY|MM|DD|df=y}} -->
| first_published  = ??
| version          = ??
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| organization      = [[Company:Intel|Intel]]
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| domain            = Hardware management
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In [[Computing|computing]], [[Company:Intel|Intel]]'s '''Advanced Programmable Interrupt Controller''' ('''APIC''') is a family of [[Programmable interrupt controller|programmable interrupt controller]]s. As its name suggests, the APIC is more advanced than Intel's 8259 Programmable Interrupt Controller (PIC), particularly enabling the construction of multiprocessor systems. It is one of several architectural designs intended to solve interrupt routing efficiency issues in multiprocessor computer systems.
In [[Computing|computing]], [[Company:Intel|Intel]]'s '''Advanced Programmable Interrupt Controller''' ('''APIC''') is a family of [[Programmable interrupt controller|programmable interrupt controller]]s. As its name suggests, the APIC is more advanced than Intel's 8259 Programmable Interrupt Controller (PIC), particularly enabling the construction of multiprocessor systems. It is one of several architectural designs intended to solve interrupt routing efficiency issues in multiprocessor computer systems.


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There are two components in the Intel APIC system, the ''local APIC'' (LAPIC) and the ''I/O APIC''. There is one LAPIC in each CPU in the system. In the very first implementation ('''82489DX'''), the LAPIC was a discrete circuit, as opposed to its later implementation in Intel processors' silicon. There is typically one I/O APIC for each peripheral bus in the system. In original system designs, LAPICs and I/O APICs were connected by a dedicated APIC bus. Newer systems use the system bus for communication between all APIC components.
There are two components in the Intel APIC system, the ''local APIC'' (LAPIC) and the ''I/O APIC''. There is one LAPIC in each CPU in the system. In the very first implementation ('''82489DX'''), the LAPIC was a discrete circuit, as opposed to its later implementation in Intel processors' silicon. There is typically one I/O APIC for each peripheral bus in the system. In original system designs, LAPICs and I/O APICs were connected by a dedicated APIC bus. Newer systems use the system bus for communication between all APIC components.


Each APIC, whether a discrete chip or integrated in a CPU, has a version register containing a four-bit version number for its specific APIC implementation. For example, the 82489DX has an APIC version number of 0, while version 1 was assigned to the first generation of local APICs integrated in the Pentium 90 and 100 processors.<ref>[http://www.intel.com/design/archives/processors/pro/docs/242016.htm Intel MultiProcessor Specification], version 1.4, page 3-5, May 1997</ref>
Each APIC, whether a discrete chip or integrated in a CPU, has a version register containing a four-bit version number for its specific APIC implementation. For example, the 82489DX has an APIC version number of 0, while version 1 was assigned to the first generation of local APICs integrated in the Pentium 90 and 100 processors.<ref name="MP-specification">{{cite web |url=http://www.intel.com/design/archives/processors/pro/docs/242016.htm |url-status=dead |archive-url=https://web.archive.org/web/20041030040529/http://www.intel.com/design/archives/processors/pro/docs/242016.htm |archive-date=October 30, 2004 |publisher=Intel |title=MultiProcessor Specification, version 1.4 |date=May 1997}}</ref>{{rp|page=3-5}}


In systems containing an [[Intel 8259|8259 PIC]], the 8259 may be connected to the LAPIC in the system's bootstrap processor (BSP), one of the system's I/O APICs, or both. Logically, however, the 8259 is only connected once at any given time.
In systems containing an [[Intel 8259|8259 PIC]], the 8259 may be connected to the LAPIC in the system's bootstrap processor (BSP), one of the system's I/O APICs, or both. Logically, however, the 8259 is only connected once at any given time.


==Discrete APIC==
==Discrete APIC==
The first-generation Intel APIC chip, the 82489DX, which was meant to be used with [[Engineering:Intel 80486|Intel 80486]] and early Pentium processors, is actually an external local and I/O APIC in one circuit. The Intel MP 1.4 specification refers to it as "discrete APIC" in contrast with the "integrated APIC" found in most of the Pentium processors.<ref>[http://www.intel.com/design/archives/processors/pro/docs/242016.htm Intel MultiProcessor Specification], version 1.4, page 1-4, May 1997</ref> The 82489DX had 16 interrupt lines;<ref name="Ram2001">{{cite book|author=Badri Ram|title=Adv Microprocessors Interfacing|url=https://books.google.com/books?id=eVcEWDIeTYcC&pg=PT314|year=2001|publisher=Tata McGraw-Hill Education|isbn=978-0-07-043448-6|page=314}}</ref> it also had a quirk that it could lose some ISA interrupts.<ref >{{cite web | website=freebsd.org|title=A Description of the APIC I/O Subsystem | url=http://people.freebsd.org/~fsmp/SMP/papers/apicsubsystem.txt | access-date=14 May 2023}}</ref>
The first-generation Intel APIC chip, the 82489DX, which was meant to be used with [[Engineering:Intel 80486|Intel 80486]] and early Pentium processors, is actually an external local and I/O APIC in one circuit. The Intel MP 1.4 specification refers to it as "discrete APIC" in contrast with the "integrated APIC" found in most of the Pentium processors.<ref name="MP-specification" />{{rp|page=1-4}} The 82489DX had 16 interrupt lines;<ref name="Ram2001">{{cite book|author=Badri Ram|title=Adv Microprocessors Interfacing|url=https://books.google.com/books?id=eVcEWDIeTYcC&pg=PT314|year=2001|publisher=Tata McGraw-Hill Education|isbn=978-0-07-043448-6|page=314}}</ref> it also had a quirk that it could lose some ISA interrupts.<ref >{{cite web | website=freebsd.org|title=A Description of the APIC I/O Subsystem | url=http://people.freebsd.org/~fsmp/SMP/papers/apicsubsystem.txt | access-date=14 May 2023}}</ref>


In a multiprocessor 486 system, each CPU had to be paired with its own 82489DX; additionally a supplementary 82489DX had to be used as I/O APIC. The 82489DX could not emulate the 8259A (XT-PIC) so these also had to be included as physical chips for backwards compatibility.<ref>Intel MultiProcessor Specification, version 1.4, page 5-3, May 1997</ref> The 82489DX was a packaged as a 132-pin PQFP.<ref name="Ram2001"/>
In a multiprocessor 486 system, each CPU had to be paired with its own 82489DX; additionally a supplementary 82489DX had to be used as I/O APIC. The 82489DX could not emulate the 8259A (XT-PIC) so these also had to be included as physical chips for backwards compatibility.<ref name="MP-specification" />{{rp|page=5-3}} The 82489DX was packaged as a 132-pin PQFP.<ref name="Ram2001"/>  It was available for USD $26 per 1,000-unit in quantities.<ref>Intel Corporation, "New Product Focus: OEM: Interrupt Controller Optimized for Advanced Operating Systems", Microcomputer Solutions, January/February 1993, page 21</ref>


==Integrated local APICs==
==Integrated local APICs==
Local APICs (LAPICs) manage all external interrupts for some specific processor in an SMP system. In addition, they are able to accept and generate [[Inter-processor interrupt|inter-processor interrupt]]s (IPIs) between LAPICs. LAPICs may support up to 224 usable [[Interrupt|interrupt]] vectors from an I/O APIC. Vector numbers 0 to 31, out of 0 to 255, are reserved for exception handling by x86 processors.
Local APICs (LAPICs) manage all external interrupts for some specific processor in an SMP system. In addition, they are able to accept and generate [[Inter-processor interrupt|inter-processor interrupt]]s (IPIs) between LAPICs. A single LAPIC may support up to 224 usable [[Interrupt|interrupt]] vectors from an I/O APIC. Vector numbers 0 to 31, out of 0 to 255, are reserved for exception handling by x86 processors.


All Intel processors starting with the P5 microarchitecture (P54C) have a built-in local APIC.<ref name="Mueller2011">{{cite book|author=Scott M. Mueller|title=Upgrading and Repairing PCs|year=2011|publisher=Que Publishing|isbn=978-0-13-268218-3|page=242|edition=20th}}</ref><ref name="timer" /> However, if the local APIC is disabled in a P5 processor, it cannot be re-enabled by software; this limitation no longer exists in the [[Engineering:P6 (microarchitecture)|P6 processors]] and later ones.<ref name="timer" />
All Intel processors starting with the P5 microarchitecture (P54C) have a built-in local APIC.<ref name="Mueller2011">{{cite book|author=Scott M. Mueller|title=Upgrading and Repairing PCs|year=2011|publisher=Que Publishing|isbn=978-0-13-268218-3|page=242|edition=20th}}</ref><ref name="timer" /> However, if the local APIC is disabled in a P5 processor, it cannot be re-enabled by software; this limitation no longer exists in the [[Engineering:P6 (microarchitecture)|P6 processors]] and later ones.<ref name="timer" />


The [[Message Signaled Interrupts]] (MSI) feature of the PCI 2.2 and later specifications cannot be used without the local APIC being enabled.<ref name="up">{{cite web|url=http://msdn.microsoft.com/en-us/windows/hardware/gg462964.aspx|title=Windows Hardware Dev Center|website=msdn.microsoft.com|date=June 2017 }}</ref> Use of MSI obviates the need for an I/O APIC. Additionally, up to 224 interrupts are supported in MSI mode, and IRQ sharing is not allowed.<ref name="msi"/>
With the introduction of Pentium 4 HT and [[Engineering:Pentium D|Pentium D]], each CPU core and each CPU thread have the integrated LAPIC.
 
The [[Message Signaled Interrupts]] (MSI) feature of the PCI 2.2 and later specifications cannot be used without the local APIC being enabled.<ref name="up">{{cite web |url=http://msdn.microsoft.com/en-us/windows/hardware/gg462964.aspx |url-status=dead |archive-url=https://web.archive.org/web/20121026064337/http://msdn.microsoft.com/en-us/windows/hardware/gg462964.aspx |archive-date=October 26, 2012 |title=APIC-Based Interrupt Subsystems on Uniprocessor PCs |date=January 7, 2003 |website=Windows Hardware Dev Center}}</ref> Use of MSI obviates the need for an I/O APIC. Additionally, up to 224 interrupts are supported in MSI mode, and IRQ sharing is not allowed.<ref name="msi"/>{{rp|pages=10-11}}


=== APIC timer ===
=== APIC timer ===
Another advantage of the local APIC is that it also provides a high-resolution (on the order of one [[Microsecond|microsecond]] or better) timer that can be used in both interval and one-off mode.<ref name="timer">Uwe Walter, Vincent Oberle [http://telematics.tm.kit.edu/publications/Files/61/walter_ibm_linux_challenge.pdf μ-second precision timer support for the Linux kernel]</ref>
Another advantage of the local APIC is that it also provides a high-resolution (on the order of one [[Microsecond|microsecond]] or better) timer that can be used in both interval and one-off mode.<ref name="timer">{{cite web |author1=Uwe Walter |author2=Vincent Oberle |url=http://telematics.tm.kit.edu/publications/Files/61/walter_ibm_linux_challenge.pdf |title=μ-second precision timer support for the Linux kernel}}</ref>


The APIC timer had its initial acceptance woes. A Microsoft document from 2002 (which advocated for the adoption of [[Engineering:High Precision Event Timer|High Precision Event Timer]] instead) criticized the LAPIC timer for having "poor resolution" and stating that "the clocks silicon is sometimes very buggy".<ref>[http://msdn.microsoft.com/en-us/library/windows/hardware/gg463347.aspx Guidelines For Providing Multimedia Timer Support], September 20, 2002</ref> Nevertheless, the APIC timer is used for example by [[Software:Windows 7|Windows 7]] when [[Profiling (computer programming)|profiling]] is enabled, and by [[Software:Windows 8|Windows 8]] in all circumstances. (Before Windows 8 claimed exclusive rights to this timer, it was also used by some programs like [[Software:CPU-Z|CPU-Z]].) Under Microsoft Windows the APIC timer is not a shareable resource.<ref>{{Cite web|url=https://social.msdn.microsoft.com/Forums/windowsdesktop/en-US/5d075378-a45f-433b-a3f7-73f974ec962f/windows-8-and-apic-timer?forum=wdk|archive-url=https://web.archive.org/web/20140222070735/http://social.msdn.microsoft.com/Forums/windowsdesktop/en-US/5d075378-a45f-433b-a3f7-73f974ec962f/windows-8-and-apic-timer?forum=wdk|url-status=dead|title=Windows 8 and APIC timer|archive-date=22 February 2014|website=social.msdn.microsoft.com|access-date=14 May 2023}}</ref>
The APIC timer had its initial acceptance woes. A Microsoft document from 2002 (which advocated for the adoption of [[Engineering:High Precision Event Timer|High Precision Event Timer]] instead) criticized the LAPIC timer for having "poor resolution" and stating that "the clocks silicon is sometimes very buggy".<ref>{{Cite web |date=2002-09-20 |title=Guidelines For Providing Multimedia Timer Support |url=http://msdn.microsoft.com/en-us/library/windows/hardware/gg463347.aspx |archive-url=https://web.archive.org/web/20120728124718/http://msdn.microsoft.com/en-us/library/windows/hardware/gg463347.aspx |archive-date=2012-07-28 |url-status=deviated |website=Microsoft}}</ref> Nevertheless, the APIC timer is used for example by [[Software:Windows 7|Windows 7]] when [[Profiling (computer programming)|profiling]] is enabled, and by [[Software:Windows 8|Windows 8]] in all circumstances. (Before Windows 8 claimed exclusive rights to this timer, it was also used by some programs like [[Software:CPU-Z|CPU-Z]].) Under Microsoft Windows the APIC timer is not a shareable resource.<ref>{{Cite web|url=https://social.msdn.microsoft.com/Forums/windowsdesktop/en-US/5d075378-a45f-433b-a3f7-73f974ec962f/windows-8-and-apic-timer?forum=wdk|archive-url=https://web.archive.org/web/20140222070735/http://social.msdn.microsoft.com/Forums/windowsdesktop/en-US/5d075378-a45f-433b-a3f7-73f974ec962f/windows-8-and-apic-timer?forum=wdk|url-status=dead|title=Windows 8 and APIC timer|archive-date=22 February 2014|website=social.msdn.microsoft.com|access-date=14 May 2023}}</ref>


The aperiodic interrupts offered by the APIC timer are used by the [[Software:Linux kernel|Linux kernel]] [[Software:Tickless kernel|tickless kernel]]
The aperiodic interrupts offered by the APIC timer are used by the [[Software:Linux kernel|Linux kernel]] [[Software:Tickless kernel|tickless kernel]]
feature. This optional but default feature is new with 2.6.18.  When enabled on a computer with an APIC timer, the kernel does not use the 8253 [[Engineering:Programmable interval timer|programmable interval timer]] for timekeeping.<ref>{{cite web|url=http://kb.vmware.com/selfservice/microsites/search.do?language=en_US&cmd=displayKC&externalId=1005802|title=VMware Knowledge Base|website=kb.vmware.com}}</ref> A [[Company:VMware|VMware]] document notes that "software does not have a reliable way to determine its frequency. Generally, the only way to determine the local APIC timer’s frequency is to measure it using the PIT or CMOS timer, which yields only an approximate result."<ref name="vmware">[http://www.vmware.com/files/pdf/Timekeeping-In-VirtualMachines.pdf Timekeeping in VMware Virtual Machines (for VMware vSphere 5.0, Workstation 8.0, Fusion 4.0)], page 8</ref>
feature. This optional but default feature is new with 2.6.18.  When enabled on a computer with an APIC timer, the kernel does not use the 8253 [[Engineering:Programmable interval timer|programmable interval timer]] for timekeeping.<ref>{{cite web|url=http://kb.vmware.com/selfservice/microsites/search.do?language=en_US&cmd=displayKC&externalId=1005802|title=VMware Knowledge Base|website=kb.vmware.com|access-date=2014-02-13|archive-date=2017-02-27|archive-url=https://web.archive.org/web/20170227025032/http://kb.vmware.com/selfservice/microsites/search.do?language=en_US&cmd=displayKC&externalId=1005802|url-status=dead}}</ref> A [[Company:VMware|VMware]] document notes that "software does not have a reliable way to determine its frequency. Generally, the only way to determine the local APIC timer’s frequency is to measure it using the PIT or CMOS timer, which yields only an approximate result."<ref name="vmware">{{cite web |url=http://www.vmware.com/files/pdf/Timekeeping-In-VirtualMachines.pdf |title=Timekeeping in VMware Virtual Machines (for VMware vSphere 5.0, Workstation 8.0, Fusion 4.0) |archive-url=https://web.archive.org/web/20160626142735/http://www.vmware.com/files/pdf/Timekeeping-In-VirtualMachines.pdf |archive-date=2016-06-26 |url-status=dead |page=8}}</ref>


==I/O APICs==
==I/O APICs==
I/O APICs contain a redirection table, which is used to route the interrupts it receives from peripheral buses to one or more local APICs. Early I/O APICs (like 82489DX, SIO.A and PCEB/ESC) only had support for 16 interrupt lines, but later ones like 82093AA (separate chip for PIIX3/PIIX4) had support for 24 interrupt lines.<ref name="msi">James Coleman, [http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/msg-signaled-interrupts-paper.pdf Reducing Interrupt Latency Through the Use of Message Signaled Interrupts], pp. 10-11</ref> It was packaged as a 64-Pin PQFP.<ref name="i82093AA">{{cite web|url=http://www.intel.com/design/chipsets/datashts/290566.htm|title=Resource & Design Center for Development with Intel|website=Intel}}</ref> The 82093AA normally connected to the PIIX3/PIIX4 and used its integrated legacy 8259 PICs.<ref name="i82093AA"/> The ICH1 and Intel 815 integrated the I/O APIC.
I/O APICs contain a redirection table, which is used to route the interrupts it receives from peripheral buses to one or more local APICs. Early I/O APICs (like 82489DX, SIO.A and PCEB/ESC) only had support for 16 interrupt lines, but later ones like 82093AA (separate chip for PIIX3/PIIX4) had support for 24 interrupt lines.<ref name="msi">{{cite web |author=James Coleman |url=http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/msg-signaled-interrupts-paper.pdf |url-status=dead |archive-url=https://web.archive.org/web/20220119161320/http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/msg-signaled-interrupts-paper.pdf |archive-date=January 19, 2022 |title=Reducing Interrupt Latency Through the Use of Message Signaled Interrupts |date=January 2009 |publisher=Intel}}</ref>{{rp|pages=10-11}} It was packaged as a 64-Pin PQFP.<ref name="i82093AA">{{cite web |url=http://www.intel.com/design/chipsets/datashts/290566.htm |url-status=dead |archive-url=https://web.archive.org/web/20161128201003/http://www.intel.com/design/chipsets/datashts/290566.htm |archive-date=November 28, 2016 |title=Intel 82093AA I/O Advanced Programmable Interrupt Controller (I/O APIC) Datasheet |website=Resource & Design Center for Development with Intel}}</ref> The 82093AA normally connected to the PIIX3/PIIX4 and used its integrated legacy 8259 PICs.<ref name="i82093AA"/> The ICH1 integrated the I/O APIC. An integrated I/O APIC of modern chipsets may provide more than 24 interrupt lines.<ref>{{cite web |url=https://cdrdv2-public.intel.com/620855/620855-002.pdf |title=Intel 400 Series Chipset Family Platform Controller Hub Datasheet - Volume 2 of 2 |date=May 2020 |publisher=[[Company:Intel|Intel]]}}</ref>


According to a 2009 Intel benchmark using [[Software:Linux|Linux]], the I/O APIC reduced interrupt latency by a factor of almost three relative to the 8259 emulation (XT-PIC), while using MSI reduced the latency even more, by a factor of nearly seven relative to the XT-PIC baseline.<ref>James Coleman, [http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/msg-signaled-interrupts-paper.pdf Reducing Interrupt Latency Through the Use of Message Signaled Interrupts], p. 19</ref>
According to a 2009 Intel benchmark using [[Software:Linux|Linux]], the I/O APIC reduced interrupt latency by a factor of almost three relative to the 8259 emulation (XT-PIC), while using MSI reduced the latency even more, by a factor of nearly seven relative to the XT-PIC baseline.<ref name="msi"/>{{rp|page=19}}


== {{Anchor|XAPIC|X2APIC}}Variants ==
== {{Anchor|XAPIC|X2APIC}}Variants ==
The ''xAPIC'' was introduced with the [[Engineering:Pentium 4|Pentium 4]], while the ''x2APIC'' is the most recent generation of the Intel's programmable interrupt controller, introduced with the [[Engineering:Nehalem (microarchitecture)|Nehalem microarchitecture]] in November 2008.<ref>{{cite web|url=http://www.computerbase.de/bildstrecke/20069/27/|title=Intel Nehalem mit X2APIC - Extended xAPIC Architecture (Bild 27/27) - ComputerBase|website=www.computerbase.de}}</ref> The major improvements of the x2APIC address the number of supported CPUs and performance of the interface.
The ''xAPIC'' was introduced with the [[Engineering:Pentium 4|Pentium 4]], while the ''x2APIC'' is the most recent generation of the Intel's programmable interrupt controller, introduced with the [[Engineering:Nehalem (microarchitecture)|Nehalem microarchitecture]] in November 2008.<ref>{{cite web |url=https://pics.computerbase.de/1/7/6/1/8/9-1080.3482223454.jpg |title=X2APIC Key Feature Enhancement |website=ComputerBase}}</ref> The major improvements of the x2APIC address the number of supported CPUs and performance of the interface.


The x2APIC now uses 32 bits to address CPUs, allowing to address up to 2<sup>32</sup>&nbsp;&minus; 1 CPUs using the physical destination mode. The logical destination mode now works differently and introduces clusters; using this mode, one can address up to 2<sup>20</sup>&nbsp;&minus; 16 processors.
The x2APIC now uses 32 bits to address CPUs, allowing to address up to 2<sup>32</sup>&nbsp;&minus; 1 CPUs using the physical destination mode. The logical destination mode now works differently and introduces clusters; using this mode, one can address up to 2<sup>20</sup>&nbsp;&minus; 16 processors.


The improved interface reduces the number of needed APIC register accesses for sending [[Inter-processor interrupt|inter-processor interrupt]]s (IPIs). Because of this advantage, [[Software:Kernel-based Virtual Machine|KVM]] can and does emulate the x2APIC for older processors that do not physically support it, and this support is exposed from [[Software:QEMU|QEMU]] going back to Conroe and even for AMD [[Engineering:Opteron|Opteron]] G-series processors (neither of which natively support x2APIC).<ref>{{cite web|url=https://lists.gnu.org/archive/html/qemu-devel/2013-07/msg03756.html|title=Re: [Qemu-devel] [Question] why x2apic's set by default without host sup|website=lists.gnu.org}}</ref><ref>{{cite web|url=http://lists.nongnu.org/archive/html/qemu-devel/2014-01/msg02441.html|title=[Qemu-devel] [PATCH] target-i386: enable x2apic by default on more recen|website=lists.nongnu.org}}</ref>
The improved interface reduces the number of needed APIC register accesses for sending [[Inter-processor interrupt|inter-processor interrupt]]s (IPIs). Because of this advantage, [[Software:Kernel-based Virtual Machine|KVM]] can and does emulate the x2APIC for older processors that do not physically support it, and this support is exposed from [[Software:QEMU|QEMU]] going back to Conroe and even for AMD [[Engineering:Opteron|Opteron]] G-series processors (neither of which natively support x2APIC).<ref>{{cite mailing list |url=https://lists.gnu.org/archive/html/qemu-devel/2013-07/msg03756.html |title=Re: [Qemu-devel] [Question] why x2apic's set by default without host support(on Nehalem CPU). |author=Marcelo Tosatti |date=July 22, 2013 |mailing-list=qemu-devel}}</ref><ref>{{cite mailing list |url=http://lists.nongnu.org/archive/html/qemu-devel/2014-01/msg02441.html |title=[Qemu-devel] [PATCH] target-i386: enable x2apic by default on more recent CPU models |author=Eduardo Habkost |date=January 20, 2014 |mailing-list=qemu-devel}}</ref>


APICv is Intel's brand name for [[Hardware virtualization|hardware virtualization]] support aimed at reducing interrupt overhead in guests. APICv was introduced in the Ivy Bridge-EP processor series, which is sold as Xeon E5-26xx v2 (launched in late 2013) and as Xeon E5-46xx v2 (launched in early 2014).<ref>{{cite web |author=Jun Nakajima |title=Reviewing Unused and New Features for Interrupt/APIC Virtualization |url=http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-intel-vt-feat-nakajima.pdf |website=Linux |access-date=14 May 2023 |year=2012}}</ref><ref>{{cite web|url=https://software.intel.com/en-us/blogs/2013/12/17/apic-virtualization-performance-testing-and-iozone|title=APIC Virtualization Performance Testing and Iozone* - Intel® Software|website=software.intel.com}}</ref> AMD announced a similar technology called AVIC,<ref>Wei Huang, [http://www.slideshare.net/xen_com_mgr/introduction-of-amd-virtual-interrupt-controller Introduction of AMD Advanced Virtual Interrupt Controller], XenSummit 2012</ref><ref>{{cite web |author=Jörg Rödel |title=Next-generation Interrupt Virtualization for KVM |url=http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-interrupt-virt-kvm-roedel.pdf |website=Linux |access-date=14 May 2023 |date=August 2012}}</ref> it is available family [[Engineering:Excavator (microarchitecture)|15h models 6Xh (Carrizo) processors]] and newer.<ref>{{cite web|url=https://www.mail-archive.com/xen-devel@lists.xen.org/msg81719.html|title=[Xen-devel] [RFC PATCH 0/9] Introduce AMD SVM AVIC|website=www.mail-archive.com}}</ref>
APICv is Intel's brand name for [[Hardware virtualization|hardware virtualization]] support aimed at reducing interrupt overhead in guests. APICv was introduced in the Ivy Bridge-EP processor series, which is sold as Xeon E5-26xx v2 (launched in late 2013) and as Xeon E5-46xx v2 (launched in early 2014).<ref>{{cite conference |author=Jun Nakajima |title=Reviewing Unused and New Features for Interrupt/APIC Virtualization |url=http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-intel-vt-feat-nakajima.pdf |conference=Linux Plumber's Conference 2012 |access-date=14 May 2023 |year=2012}}</ref><ref>{{cite web|url=https://software.intel.com/en-us/blogs/2013/12/17/apic-virtualization-performance-testing-and-iozone|title=APIC Virtualization Performance Testing and Iozone* - Intel® Software|website=software.intel.com}}</ref> AMD announced a similar technology called AVIC,<ref>{{cite conference |author=Wei Huang |url=http://www.slideshare.net/xen_com_mgr/introduction-of-amd-virtual-interrupt-controller |title=Introduction of AMD Advanced Virtual Interrupt Controller |conference=XenSummit 2012}}</ref><ref>{{cite conference |author=Jörg Rödel |title=Next-generation Interrupt Virtualization for KVM |url=http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-interrupt-virt-kvm-roedel.pdf |conference=Linux Plumber's Conference 2012 |access-date=14 May 2023 |date=August 2012}}</ref> it is available family [[Engineering:Excavator (microarchitecture)|15h models 6Xh (Carrizo) processors]] and newer.<ref>{{cite mailing list |url=https://www.mail-archive.com/xen-devel@lists.xen.org/msg81719.html |title=[Xen-devel] [RFC PATCH 0/9] Introduce AMD SVM AVIC |author=Suravee Suthikulpanit |date=September 18, 2016 |mailing-list=Xen-devel}}</ref>


== Issues ==
== Issues ==
Line 52: Line 84:


== Competition ==
== Competition ==
[[Engineering:AMD|AMD]] and [[Company:Cyrix|Cyrix]] once proposed a somewhat similar-in-purpose OpenPIC architecture supporting up to 32 processors;<ref>{{cite web|url=https://www.pcmag.com/encyclopedia_term/0,2542,t=OpenPIC&i=48497,00.asp |title=OpenPIC Definition from PC Magazine Encyclopedia |publisher=Pcmag.com |date=1994-12-01 |access-date=2011-11-03}}</ref> it had at least declarative support from [[Company:IBM|IBM]] and [[Company:Compaq|Compaq]] around 1995.<ref name="Inc.1995">{{cite journal|title=AMD, Cyrix offer up alternative SMP spec|author=Brooke Crothers|journal=InfoWorld|url=https://books.google.com/books?id=lToEAAAAMBAJ&pg=PA8|date=20 March 1995|page=8|issn=0199-6649}}</ref> No x86 motherboard was released with OpenPIC however.<ref>André D. Balsa, [http://linuxgazette.net/issue24/Article3e-7.html Note attached to "Linux Benchmarking: Part III -- Interpreting Benchmark Results"] appearing in Issue 24 of Linux Gazette, January 1998</ref> After the OpenPIC's failure in the x86 market, AMD licensed Intel's APIC for its AMD Athlon and later processors.
[[Engineering:AMD|AMD]] and [[Company:Cyrix|Cyrix]] once proposed a somewhat similar-in-purpose OpenPIC architecture supporting up to 32 processors;<ref>{{cite web |url=https://www.pcmag.com/encyclopedia/term/openpic |title=OpenPIC Definition from PC Magazine Encyclopedia |publisher=Pcmag.com |date=1994-12-01 |access-date=2025-09-24}}</ref> it had at least declarative support from [[Company:IBM|IBM]] and [[Company:Compaq|Compaq]] around 1995.<ref name="Inc.1995">{{cite journal|title=AMD, Cyrix offer up alternative SMP spec|author=Brooke Crothers|journal=InfoWorld|url=https://books.google.com/books?id=lToEAAAAMBAJ&pg=PA8|date=20 March 1995|page=8|issn=0199-6649}}</ref> No x86 motherboard was released with OpenPIC however.<ref>{{cite web |author=André D. Balsa |url=http://linuxgazette.net/issue24/Article3e-7.html |title=Note attached to "Linux Benchmarking: Part III -- Interpreting Benchmark Results"] appearing in Issue 24 of Linux Gazette, January 1998}}</ref> After the OpenPIC's failure in the x86 market, AMD licensed Intel's APIC for its AMD Athlon and later processors.


IBM however developed their [[OpenPIC and MPIC|MultiProcessor Interrupt Controller]] (MPIC) based on the OpenPIC register specifications.<ref>IBM [https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/$file/mpic_db_05_16_2011.pdf Multiprocessor Interrupt Controller. Data Book] {{webarchive|url=https://web.archive.org/web/20140223012746/https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/%24file/mpic_db_05_16_2011.pdf |date=2014-02-23 }}</ref> MPIC was used in [[PowerPC]] based designs, including those of IBM, for instance in some RS/6000 systems,<ref>Arca Systems TTAP Evaluation Facility [http://www.ashtonlabs.com/library/FERs/CSC-FER-98-004.pdf The IBM Corporation RS/6000 Distributed System Running AIX Version 4.3.1. TCSEC Evaluated C2 Security], p. 29</ref> but also by Apple, as late as their Power Mac G5s.<ref>{{cite book|url=http://www.informit.com/articles/article.aspx?p=606582|title=Take a Look Inside the G5-Based Dual-Processor Power Mac|first=Amit|last=Singh|date=13 October 2006|via=informIT database}}</ref><ref>[https://developer.apple.com/legacy/library/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/PowerMacG5.pdf Power Mac G5 Developer Note (Legacy)], p. 26</ref>
IBM however developed their [[OpenPIC and MPIC|MultiProcessor Interrupt Controller]] (MPIC) based on the OpenPIC register specifications.<ref>{{cite web |publisher=IBM |url=https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/$file/mpic_db_05_16_2011.pdf |title=Multiprocessor Interrupt Controller. Data Book |archive-url=https://web.archive.org/web/20140223012746/https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/%24file/mpic_db_05_16_2011.pdf |archive-date=2014-02-23 |url-status=dead}}</ref> MPIC was used in [[PowerPC]] based designs, including those of IBM, for instance in some RS/6000 systems,<ref>{{cite web |publisher=Arca Systems TTAP Evaluation Facility |url=http://www.ashtonlabs.com/library/FERs/CSC-FER-98-004.pdf |title=The IBM Corporation RS/6000 Distributed System Running AIX Version 4.3.1. TCSEC Evaluated C2 Security |page=29}}</ref> but also by Apple, as late as their Power Mac G5s.<ref>{{cite book|url=http://www.informit.com/articles/article.aspx?p=606582|title=Take a Look Inside the G5-Based Dual-Processor Power Mac|first=Amit|last=Singh|date=13 October 2006|via=informIT database}}</ref><ref>{{cite web |url=https://developer.apple.com/library/archive/documentation/Hardware/Conceptual/PowerMac_G5_05Oct/Articles/PwrMacG5-0510_archi.html#//apple_ref/doc/uid/TP40003917-TPXREF119 |title=Power Mac G5 Developer Note |at=Interrupt Support |website=Apple Developer}}</ref>


== See also ==
== See also ==
Line 72: Line 104:
== External links ==
== External links ==
* [http://www.intel.com/content/dam/doc/specification-update/64-architecture-x2apic-specification.pdf Intel 64 Architecture x2APIC Specification] (PDF)
* [http://www.intel.com/content/dam/doc/specification-update/64-architecture-x2apic-specification.pdf Intel 64 Architecture x2APIC Specification] (PDF)
* More information on the Intel x2APIC Architecture can be found in the ''Intel 64 and IA-32 [http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html Architectures Software Developer's Manuals]
* More information on the Intel x2APIC Architecture can be found in the ''Intel 64 and IA-32 [http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html Architectures Software Developer's Manuals]''
{{Intel}}
{{Intel}}


Latest revision as of 03:10, 24 May 2026

Short description: Family of computer interrupt controllers
Advanced Programmable Interrupt Controller
StatusActive
First published??
Latest version??
??
OrganizationIntel
DomainHardware management
AbbreviationAPIC
Website??

In computing, Intel's Advanced Programmable Interrupt Controller (APIC) is a family of programmable interrupt controllers. As its name suggests, the APIC is more advanced than Intel's 8259 Programmable Interrupt Controller (PIC), particularly enabling the construction of multiprocessor systems. It is one of several architectural designs intended to solve interrupt routing efficiency issues in multiprocessor computer systems.

The APIC is a split architecture design, with a local component (LAPIC) usually integrated into the processor itself, and an optional I/O APIC on a system bus. The first APIC was the 82489DX – it was a discrete chip that functioned both as local and I/O APIC. The 82489DX enabled construction of symmetric multiprocessor (SMP) systems with the Intel 486 and early Pentium processors; for example, the reference two-way 486 SMP system used three 82489DX chips, two as local APICs and one as I/O APIC. Starting with the P54C processor, the local APIC functionality was integrated into the Intel processors' silicon. The first dedicated I/O APIC was the Intel 82093AA, which was intended for PIIX3-based systems.

Overview

There are two components in the Intel APIC system, the local APIC (LAPIC) and the I/O APIC. There is one LAPIC in each CPU in the system. In the very first implementation (82489DX), the LAPIC was a discrete circuit, as opposed to its later implementation in Intel processors' silicon. There is typically one I/O APIC for each peripheral bus in the system. In original system designs, LAPICs and I/O APICs were connected by a dedicated APIC bus. Newer systems use the system bus for communication between all APIC components.

Each APIC, whether a discrete chip or integrated in a CPU, has a version register containing a four-bit version number for its specific APIC implementation. For example, the 82489DX has an APIC version number of 0, while version 1 was assigned to the first generation of local APICs integrated in the Pentium 90 and 100 processors.[1]: 3-5 

In systems containing an 8259 PIC, the 8259 may be connected to the LAPIC in the system's bootstrap processor (BSP), one of the system's I/O APICs, or both. Logically, however, the 8259 is only connected once at any given time.

Discrete APIC

The first-generation Intel APIC chip, the 82489DX, which was meant to be used with Intel 80486 and early Pentium processors, is actually an external local and I/O APIC in one circuit. The Intel MP 1.4 specification refers to it as "discrete APIC" in contrast with the "integrated APIC" found in most of the Pentium processors.[1]: 1-4  The 82489DX had 16 interrupt lines;[2] it also had a quirk that it could lose some ISA interrupts.[3]

In a multiprocessor 486 system, each CPU had to be paired with its own 82489DX; additionally a supplementary 82489DX had to be used as I/O APIC. The 82489DX could not emulate the 8259A (XT-PIC) so these also had to be included as physical chips for backwards compatibility.[1]: 5-3  The 82489DX was packaged as a 132-pin PQFP.[2] It was available for USD $26 per 1,000-unit in quantities.[4]

Integrated local APICs

Local APICs (LAPICs) manage all external interrupts for some specific processor in an SMP system. In addition, they are able to accept and generate inter-processor interrupts (IPIs) between LAPICs. A single LAPIC may support up to 224 usable interrupt vectors from an I/O APIC. Vector numbers 0 to 31, out of 0 to 255, are reserved for exception handling by x86 processors.

All Intel processors starting with the P5 microarchitecture (P54C) have a built-in local APIC.[5][6] However, if the local APIC is disabled in a P5 processor, it cannot be re-enabled by software; this limitation no longer exists in the P6 processors and later ones.[6]

With the introduction of Pentium 4 HT and Pentium D, each CPU core and each CPU thread have the integrated LAPIC.

The Message Signaled Interrupts (MSI) feature of the PCI 2.2 and later specifications cannot be used without the local APIC being enabled.[7] Use of MSI obviates the need for an I/O APIC. Additionally, up to 224 interrupts are supported in MSI mode, and IRQ sharing is not allowed.[8]: 10–11 

APIC timer

Another advantage of the local APIC is that it also provides a high-resolution (on the order of one microsecond or better) timer that can be used in both interval and one-off mode.[6]

The APIC timer had its initial acceptance woes. A Microsoft document from 2002 (which advocated for the adoption of High Precision Event Timer instead) criticized the LAPIC timer for having "poor resolution" and stating that "the clocks silicon is sometimes very buggy".[9] Nevertheless, the APIC timer is used for example by Windows 7 when profiling is enabled, and by Windows 8 in all circumstances. (Before Windows 8 claimed exclusive rights to this timer, it was also used by some programs like CPU-Z.) Under Microsoft Windows the APIC timer is not a shareable resource.[10]

The aperiodic interrupts offered by the APIC timer are used by the Linux kernel tickless kernel feature. This optional but default feature is new with 2.6.18. When enabled on a computer with an APIC timer, the kernel does not use the 8253 programmable interval timer for timekeeping.[11] A VMware document notes that "software does not have a reliable way to determine its frequency. Generally, the only way to determine the local APIC timer’s frequency is to measure it using the PIT or CMOS timer, which yields only an approximate result."[12]

I/O APICs

I/O APICs contain a redirection table, which is used to route the interrupts it receives from peripheral buses to one or more local APICs. Early I/O APICs (like 82489DX, SIO.A and PCEB/ESC) only had support for 16 interrupt lines, but later ones like 82093AA (separate chip for PIIX3/PIIX4) had support for 24 interrupt lines.[8]: 10–11  It was packaged as a 64-Pin PQFP.[13] The 82093AA normally connected to the PIIX3/PIIX4 and used its integrated legacy 8259 PICs.[13] The ICH1 integrated the I/O APIC. An integrated I/O APIC of modern chipsets may provide more than 24 interrupt lines.[14]

According to a 2009 Intel benchmark using Linux, the I/O APIC reduced interrupt latency by a factor of almost three relative to the 8259 emulation (XT-PIC), while using MSI reduced the latency even more, by a factor of nearly seven relative to the XT-PIC baseline.[8]: 19 

Variants

The xAPIC was introduced with the Pentium 4, while the x2APIC is the most recent generation of the Intel's programmable interrupt controller, introduced with the Nehalem microarchitecture in November 2008.[15] The major improvements of the x2APIC address the number of supported CPUs and performance of the interface.

The x2APIC now uses 32 bits to address CPUs, allowing to address up to 232 − 1 CPUs using the physical destination mode. The logical destination mode now works differently and introduces clusters; using this mode, one can address up to 220 − 16 processors.

The improved interface reduces the number of needed APIC register accesses for sending inter-processor interrupts (IPIs). Because of this advantage, KVM can and does emulate the x2APIC for older processors that do not physically support it, and this support is exposed from QEMU going back to Conroe and even for AMD Opteron G-series processors (neither of which natively support x2APIC).[16][17]

APICv is Intel's brand name for hardware virtualization support aimed at reducing interrupt overhead in guests. APICv was introduced in the Ivy Bridge-EP processor series, which is sold as Xeon E5-26xx v2 (launched in late 2013) and as Xeon E5-46xx v2 (launched in early 2014).[18][19] AMD announced a similar technology called AVIC,[20][21] it is available family 15h models 6Xh (Carrizo) processors and newer.[22]

Issues

There are a number of known bugs in implementations of APIC systems, especially with concern to how the 8254 is connected. Defective BIOSes may not set up interrupt routing properly, or provide incorrect ACPI tables and Intel MultiProcessor Specification (MPS) tables.

The APIC can also be a cause of system failure when the operating system does not support it properly. On older operating systems, the I/O and local APICs often had to be disabled. While this is not possible anymore due to the prevalence of symmetric multiprocessor and multi-core systems, the bugs in the firmware and the operating systems are now a rare occurrence.

Competition

AMD and Cyrix once proposed a somewhat similar-in-purpose OpenPIC architecture supporting up to 32 processors;[23] it had at least declarative support from IBM and Compaq around 1995.[24] No x86 motherboard was released with OpenPIC however.[25] After the OpenPIC's failure in the x86 market, AMD licensed Intel's APIC for its AMD Athlon and later processors.

IBM however developed their MultiProcessor Interrupt Controller (MPIC) based on the OpenPIC register specifications.[26] MPIC was used in PowerPC based designs, including those of IBM, for instance in some RS/6000 systems,[27] but also by Apple, as late as their Power Mac G5s.[28][29]

See also

References

  1. ↑ 1.0 1.1 1.2 "MultiProcessor Specification, version 1.4". Intel. May 1997. http://www.intel.com/design/archives/processors/pro/docs/242016.htm. 
  2. ↑ 2.0 2.1 Badri Ram (2001). Adv Microprocessors Interfacing. Tata McGraw-Hill Education. p. 314. ISBN 978-0-07-043448-6. https://books.google.com/books?id=eVcEWDIeTYcC&pg=PT314. 
  3. ↑ "A Description of the APIC I/O Subsystem". http://people.freebsd.org/~fsmp/SMP/papers/apicsubsystem.txt. 
  4. ↑ Intel Corporation, "New Product Focus: OEM: Interrupt Controller Optimized for Advanced Operating Systems", Microcomputer Solutions, January/February 1993, page 21
  5. ↑ Scott M. Mueller (2011). Upgrading and Repairing PCs (20th ed.). Que Publishing. p. 242. ISBN 978-0-13-268218-3. 
  6. ↑ 6.0 6.1 6.2 "μ-second precision timer support for the Linux kernel". http://telematics.tm.kit.edu/publications/Files/61/walter_ibm_linux_challenge.pdf. 
  7. ↑ "APIC-Based Interrupt Subsystems on Uniprocessor PCs". January 7, 2003. http://msdn.microsoft.com/en-us/windows/hardware/gg462964.aspx. 
  8. ↑ 8.0 8.1 8.2 James Coleman (January 2009). "Reducing Interrupt Latency Through the Use of Message Signaled Interrupts". Intel. http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/msg-signaled-interrupts-paper.pdf. 
  9. ↑ "Guidelines For Providing Multimedia Timer Support". 2002-09-20. http://msdn.microsoft.com/en-us/library/windows/hardware/gg463347.aspx. 
  10. ↑ "Windows 8 and APIC timer". https://social.msdn.microsoft.com/Forums/windowsdesktop/en-US/5d075378-a45f-433b-a3f7-73f974ec962f/windows-8-and-apic-timer?forum=wdk. 
  11. ↑ "VMware Knowledge Base". http://kb.vmware.com/selfservice/microsites/search.do?language=en_US&cmd=displayKC&externalId=1005802. 
  12. ↑ "Timekeeping in VMware Virtual Machines (for VMware vSphere 5.0, Workstation 8.0, Fusion 4.0)". p. 8. http://www.vmware.com/files/pdf/Timekeeping-In-VirtualMachines.pdf. 
  13. ↑ 13.0 13.1 "Intel 82093AA I/O Advanced Programmable Interrupt Controller (I/O APIC) Datasheet". http://www.intel.com/design/chipsets/datashts/290566.htm. 
  14. ↑ "Intel 400 Series Chipset Family Platform Controller Hub Datasheet - Volume 2 of 2". Intel. May 2020. https://cdrdv2-public.intel.com/620855/620855-002.pdf. 
  15. ↑ "X2APIC Key Feature Enhancement". https://pics.computerbase.de/1/7/6/1/8/9-1080.3482223454.jpg. 
  16. ↑ Marcelo Tosatti (July 22, 2013). "Re: [Qemu-devel] [Question] why x2apic's set by default without host support(on Nehalem CPU)". qemu-devel (Mailing list).
  17. ↑ Eduardo Habkost (January 20, 2014). "[Qemu-devel] [PATCH] target-i386: enable x2apic by default on more recent CPU models". qemu-devel (Mailing list).
  18. ↑ Jun Nakajima (2012). "Reviewing Unused and New Features for Interrupt/APIC Virtualization". Linux Plumber's Conference 2012. http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-intel-vt-feat-nakajima.pdf. Retrieved 14 May 2023. 
  19. ↑ "APIC Virtualization Performance Testing and Iozone* - Intel® Software". https://software.intel.com/en-us/blogs/2013/12/17/apic-virtualization-performance-testing-and-iozone. 
  20. ↑ Wei Huang. "Introduction of AMD Advanced Virtual Interrupt Controller". XenSummit 2012. http://www.slideshare.net/xen_com_mgr/introduction-of-amd-virtual-interrupt-controller. 
  21. ↑ Jörg Rödel (August 2012). "Next-generation Interrupt Virtualization for KVM". Linux Plumber's Conference 2012. http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-interrupt-virt-kvm-roedel.pdf. Retrieved 14 May 2023. 
  22. ↑ Suravee Suthikulpanit (September 18, 2016). "[Xen-devel] [RFC PATCH 0/9] Introduce AMD SVM AVIC". Xen-devel (Mailing list).
  23. ↑ "OpenPIC Definition from PC Magazine Encyclopedia". Pcmag.com. 1994-12-01. https://www.pcmag.com/encyclopedia/term/openpic. 
  24. ↑ Brooke Crothers (20 March 1995). "AMD, Cyrix offer up alternative SMP spec". InfoWorld: 8. ISSN 0199-6649. https://books.google.com/books?id=lToEAAAAMBAJ&pg=PA8. 
  25. ↑ André D. Balsa. "Note attached to "Linux Benchmarking: Part III -- Interpreting Benchmark Results" appearing in Issue 24 of Linux Gazette, January 1998"]. http://linuxgazette.net/issue24/Article3e-7.html. 
  26. ↑ "Multiprocessor Interrupt Controller. Data Book". IBM. https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/$file/mpic_db_05_16_2011.pdf. 
  27. ↑ "The IBM Corporation RS/6000 Distributed System Running AIX Version 4.3.1. TCSEC Evaluated C2 Security". Arca Systems TTAP Evaluation Facility. p. 29. http://www.ashtonlabs.com/library/FERs/CSC-FER-98-004.pdf. 
  28. ↑ Singh, Amit (13 October 2006). Take a Look Inside the G5-Based Dual-Processor Power Mac. http://www.informit.com/articles/article.aspx?p=606582. 
  29. ↑ "Power Mac G5 Developer Note". Interrupt Support. https://developer.apple.com/library/archive/documentation/Hardware/Conceptual/PowerMac_G5_05Oct/Articles/PwrMacG5-0510_archi.html#//apple_ref/doc/uid/TP40003917-TPXREF119. 

Further reading



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