Engineering:Zen 3

Short description: 2020 AMD 7-nanometre processor microarchitecture

AMD Zen 3

General Info
Launched	November 5, 2020 (November 5, 2020)
Designed by	AMD
Common manufacturer(s)	TSMC (core die) GlobalFoundries (I/O die)
Cache
L1 cache	64 KB per core
L2 cache	512 KB per core
L3 cache	32 MB per CCX 96 MB with stacked L3 16 MB in APUs
Architecture and classification
Min. feature size	TSMC 7 nm TSMC 6 nm FF
Instruction set	AMD64 (x86_64)
Physical specifications
Cores	4 to 16 (desktop), up to 64 HEDT, WS, server
Package(s)	Package FP6
Socket(s)	Socket AM4 Socket SP3 Socket sWRX8
Products, models, variants
Product code name(s)	Vermeer (desktop w/o iGPU) Cézanne (mobile & desktop w/ iGPU) Rembrandt (mobile refresh) Milan (server)
History
Predecessor	Zen 2
Successor	Zen 4

Zen 3 is the codename for a CPU microarchitecture by AMD, released on November 5, 2020. It is the successor to Zen 2 and uses TSMC's 7 nm process for the chiplets and GlobalFoundries's 14 nm process for the I/O die on the server chips and 12 nm for desktop chips. Zen 3 powers Ryzen 5000 mainstream desktop processors (codenamed "Vermeer") and Epyc server processors (codenamed "Milan"). Zen 3 is supported on motherboards with 500 series chipsets; 400 series boards also saw support on select B450 / X470 motherboards with certain BIOSes. Zen 3 is expected to be the last microarchitecture before AMD switches to DDR5 memory and new sockets. According to AMD, Zen 3 has a 19% higher instructions per cycle (IPC) on average than Zen 2. On April 1, 2022, AMD released the new Ryzen 6000 series for the laptop, using an improved “Zen 3+” architecture, bringing RDNA 2 graphics integrated in a APU to the PC for the first time. On 20 April 2022 AMD also released the 5800X3D which increases the single threading performance by another 15% in gaming by using, for the first time in a PC product, 3D vertically stacked L3 cache.

Features

Zen 3 is a significant incremental improvement over its predecessors, with an IPC increase of 19%, and being capable of reaching higher clock speeds.

Like Zen 2, Zen 3 is composed of up to 2 core complex dies (CCD) along with a separate IO die containing the I/O components. A Zen 3 CCD is composed of a single core complex (CCX) containing 8 CPU cores and 32 MB of shared L3 cache, this is in contrast to Zen 2 where each CCD is composed of 2 CCX, each containing 4 cores each as well as 16 MB of L3 cache. The new configuration allows all 8 cores of the CCX to directly communicate with each other and the L3 Cache instead of having to use the IO die through the Infinity Fabric.

Zen 3 (along with AMD's RDNA2 GPUs) were also the first implementation of Resizable BAR, an optional feature introduced in PCIe 2.0, that was branded as Smart Access Memory (SAM). This technology allows CPU to directly access all of compatible video card's VRAM. Intel and Nvidia have since implemented this feature as well.

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  A de-lidded Ryzen 5 5600X. Only one CCD is present. The contacts for a second CCD are visible.

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  Close-up of the CCD, taken under infrared lighting. This die was damaged by the de-lidding process.

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  Close-up of the I/O die

In Zen 3, a single 32MB L3 cache pool is shared among all 8 cores in a chiplet, vs. Zen 2's two 16MB pools each shared among 4 cores in a core complex, of which there were two per chiplet. This new arrangement improves the cache hit rate as well as performance in situations that require cache data to be exchanged among cores, but increases cache latency from 39 cycles in Zen 2 to 46 clock cycles and halves per-core cache bandwidth, although both problems are partially mitigated by higher clock speeds. Total cache bandwidth on all 8 cores combined remains the same due to power consumption concerns. L2 cache capacity and latency remain the same at 512KB and 12 cycles. All cache read and write operations are done at 32 bytes per cycle.

Ryzen 6000 series, which was later released on April 1, 2022, introduced PCI-E 4.0 and DDR5/LPDDR5 for the first time in an APU for the laptop and also introduced RDNA2 APU graphics to the PC.

On 20 April 2022 AMD released the last member of the AM4 family, the 5800X3D. It features, for the first time in a desktop PC product, 3D stacked vertical L3 cache, which in the size of an extra 64 MB on top of the usual 32 MB increases the total amount to 96 MB and brings tremendous performance improvements for gaming, rivalling the newest processors of the competition while being much more power efficient.

Improvements

Zen 3 has made the following improvements over Zen 2:

• An increase of 19% in instructions per clock
• The base core chiplet has a single eight-core complex (versus two four-core complexes in Zen 2)
• A unified 32MB L3 cache pool equally available to all 8 cores in a chiplet, vs Zen 2's two 16MB pools each shared among 4 cores in a core complex.
  • On mobile: A unified 16MB L3
• A unified 8-core CCX (from 2x 4-Core CCX per CCD)
• Increased branch prediction bandwidth. L1 branch target buffer size increased to 1024 entries (vs 512 in Zen 2)
• New Instructions
  • VAES - 256-bit Vector AES instructions
  • INVLPGB - Broadcast TLB flushing
  • CET_SS - Control-flow Enforcement Technology / Shadow Stack
• Improved integer units
  • 96 entry integer scheduler (up from 92)
  • 192 entry physical register file (up from 180)
  • 10 issue per cycle (up from 7)
  • 256 entry reorder-buffer (up from 224)
  • fewer cycles for DIV/IDIV ops (10...20 from 16...46)
• Improved floating point units
  • 6 µOP dispatch width (up from 4)
  • FMA latency reduced by 1 cycle (down from 5 to 4)
• RDNA 2 graphics with up to 12 Compute Units (up from 8) in Ryzen 6000 series
• DDR5/LPDDR5 support (Ryzen 6000)
• Additional 64MB 3D vertically stacked dense library L3 cache (5800X3D)

Feature tables

CPUs

CPU features table

APUs

APU features table

Products

thumb|200px|AMD Ryzen 7 5800X On October 8, 2020, AMD announced four Zen 3-based desktop Ryzen processors, consisting of one Ryzen 5, one Ryzen 7, and two Ryzen 9 CPUs and featuring between 6 and 16 cores.

Desktop CPUs

The Ryzen 5000 series desktop CPUs are codenamed Vermeer, except for the Ryzen 5 5500, which is a Cezanne APU with its integrated GPU disabled. Meanwhile the Ryzen Threadripper Pro 5000 series were codenamed Chagall.

Epyc microprocessors

The Epyc server line of chips based on Zen 3 is named Milan and is the final generation of chips using the SP3 socket. Epyc Milan was released on March 15, 2021.