EEPROM

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Short description: Computer memory used for small quantities of data
A cross section of legacy EPROM structure.
Upper insulator: ONO
Lower insulator: tunnel oxide
STMicro M24C02 I²C serial type EEPROM
Atmel AT93C46A die
AT90USB162 MCU integrates 512 Byte EEPROM

EEPROM or E2PROM (electrically erasable programmable read-only memory) is a type of non-volatile memory. It is used in computers, usually integrated in microcontrollers such as smart cards and remote keyless systems, or as a separate chip device, to store relatively small amounts of data by allowing individual bytes to be erased and reprogrammed.

EEPROMs are organized as arrays of floating-gate transistors. EEPROMs can be programmed and erased in-circuit, by applying special programming signals. Originally, EEPROMs were limited to single-byte operations, which made them slower, but modern EEPROMs allow multi-byte page operations. An EEPROM has a limited life for erasing and reprogramming, reaching a million operations in modern EEPROMs. In an EEPROM that is frequently reprogrammed, the life of the EEPROM is an important design consideration.

Flash memory is a type of EEPROM designed for high speed and high density, at the expense of large erase blocks (typically 512 bytes or larger) and limited number of write cycles (often 10,000). There is no clear boundary dividing the two, but the term "EEPROM" is generally used to describe non-volatile memory with small erase blocks (as small as one byte) and a long lifetime (typically 1,000,000 cycles). Many past microcontrollers included both (flash memory for the firmware and a small EEPROM for parameters), though the trend with modern microcontrollers is to emulate EEPROM using flash.

As of 2020, flash memory costs much less than byte-programmable EEPROM and is the dominant memory type wherever a system requires a significant amount of non-volatile solid-state storage. EEPROMs, however, are still used on applications that only require small amounts of storage, like in serial presence detect.[1][2]

History

Charging mechanism of today's NOR-type FLASH memory cell. Å = 10-10 m.
Discharging mechanism of today's NOR-type FLASH memory cell

In the early 1970s, some studies, inventions, and development for electrically re-programmable non-volatile memories were performed by various companies and organizations. In 1971, the earliest research report was presented at the 3rd Conference on Solid State Devices, Tokyo in Japan by Yasuo Tarui, Yutaka Hayashi, and Kiyoko Nagai at Electrotechnical Laboratory; a Japanese national research institute.[3] They fabricated an EEPROM device in 1972,[4] and continued this study for more than 10 years.[5] These papers have been repeatedly cited by later papers and patents.[6][7]

One of their research studies includes MONOS (metal-oxide-nitride-oxide-semiconductor) technology,[8] which used Renesas Electronics' flash memory integrated in single-chip microcontrollers.[9][10][11]

In 1972, a type of electrically re-programmable non-volatile memory was invented by Fujio Masuoka at Toshiba, who is also known as the inventor of flash memory.[12] Most of the major semiconductor manufactures, such as Toshiba,[12][6] Sanyo (later, ON Semiconductor),[13] IBM,[14] Intel,[15][16] NEC (later, Renesas Electronics),[17] Philips (later, NXP Semiconductors),[18] Siemens (later, Infineon Technologies),[19] Honeywell (later, Atmel),[20] Texas Instruments,[21] studied, invented, and manufactured some electrically re-programmable non-volatile devices until 1977.

The theoretical basis of these devices is Avalanche hot-carrier injection. But in general, programmable memories, including EPROM, of early 1970s had reliability and endurance problems such as the data retention periods and the number of erase/write cycles.[22]

In 1975, NEC's semiconductor operations unit, later NEC Electronics, currently Renesas Electronics, applied the trademark name EEPROM® to the Japan Patent Office.[23][24] In 1978, this trademark right is granted and registered as No.1,342,184 in Japan, and still survives as of March 2018.

In February 1977, Eliyahou Harari at Hughes Aircraft Company invented a new EEPROM technology using Fowler-Nordheim tunnelling through a thin silicon dioxide layer between the floating-gate and the wafer. Hughes went on to produce this new EEPROM devices.[25] However, this patent[26] cited IBM's contribution of EEPROM technology and NEC's EEPROM® invention.[27][17]

In May 1977, some important research result was disclosed by Fairchild and Siemens. They used SONOS (polysilicon-oxynitride-nitride-oxide-silicon) structure with thickness of silicon dioxide less than 30 Å, and SIMOS (stacked-gate injection MOS) structure, respectively, for using Fowler-Nordheim tunnelling hot-carrier injection.[28][29]

Around 1976 to 1978, Intel's team, including George Perlegos, made some inventions to improve this tunneling E2PROM technology.[30][31] In 1978, they developed a 16K (2K word × 8) bit Intel 2816 chip with a thin silicon dioxide layer, which was less than 200 Å.[32] In 1980, this structure was publicly introduced as FLOTOX; floating gate tunnel oxide.[33] The FLOTOX structure improved reliability of erase/write cycles per byte up to 10,000 times.[34] But this device required additional 20–22V VPP bias voltage supply for byte erase, except for 5V read operations.[35]:5-86 In 1981, Perlegos and 2 other members left Intel to form Seeq Technology,[36] which used on-device charge pumps to supply the high voltages necessary for programming E2PROMs. In 1984, Perlogos left Seeq Technology to found Atmel, then Seeq Technology was acquired by Atmel.[37][38]

Theoretical basis of FLOTOX structure

As is described in former section, old EEPROMs are based on avalanche breakdown-based hot-carrier injection with high reverse breakdown voltage. But FLOTOX theoretical basis is Fowler–Nordheim tunneling hot-carrier injection through a thin silicon dioxide layer between the floating gate and the wafer. In other words, it uses a tunnel junction.[39]

Theoretical basis of the physical phenomenon itself is the same as today's flash memory. But each FLOTOX structure is in conjunction with another read-control transistor because the floating gate itself is just programming and erasing one data bit.[40]

Intel's FLOTOX device structure improved EEPROM reliability, in other words, the endurance of the write and erase cycles, and the data retention period. A material of study for single-event effect about FLOTOX is available.[41]

Today, a detailed academical explanation of FLOTOX device structure can be found in various materials.[42][43][44]

Today's EEPROM structure

Nowadays, EEPROM is used for embedded microcontrollers as well as standard EEPROM products. EEPROM still requires a 2-transistor structure per bit to erase a dedicated byte in the memory, while flash memory has 1 transistor per bit to erase a region of the memory.[45]

Security protections

Inside of a SIM card

Because EEPROM technology is used for some security gadgets, such as credit card, SIM card, key-less entry, etc., some devices have security protection mechanisms, such as copy-protection.[45][46]

Electrical interface

EEPROM devices use a serial or parallel interface for data input/output.

Serial bus devices

The common serial interfaces are SPI, I²C, Microwire, UNI/O, and 1-Wire. These use from 1 to 4 device pins and allow devices to use packages with 8 pins or less.

A typical EEPROM serial protocol consists of three phases: OP-code phase, address phase and data phase. The OP-code is usually the first 8 bits input to the serial input pin of the EEPROM device (or with most I²C devices, is implicit); followed by 8 to 24 bits of addressing, depending on the depth of the device, then the read or write data.

Each EEPROM device typically has its own set of OP-code instructions mapped to different functions. Common operations on SPI EEPROM devices are:

  • Write enable (WRENAL)
  • Write disable (WRDI)
  • Read status register (RDSR)
  • Write status register (WRSR)
  • Read data (READ)
  • Write data (WRITE)

Other operations supported by some EEPROM devices are:

  • Program
  • Sector erase
  • Chip erase commands

Parallel bus devices

Parallel EEPROM devices typically have an 8-bit data bus and an address bus wide enough to cover the complete memory. Most devices have chip select and write protect pins. Some microcontrollers also have integrated parallel EEPROM.

Operation of a parallel EEPROM is simple and fast when compared to serial EEPROM, but these devices are larger due to the higher pin count (28 pins or more) and have been decreasing in popularity in favor of serial EEPROM or flash.

Other devices

EEPROM memory is used to enable features in other types of products that are not strictly memory products. Products such as real-time clocks, digital potentiometers, digital temperature sensors, among others, may have small amounts of EEPROM to store calibration information or other data that needs to be available in the event of power loss. It was also used on video game cartridges to save game progress and configurations, before the usage of external and internal flash memories.

Failure modes

There are two limitations of stored information: endurance and data retention.

During rewrites, the gate oxide in the floating-gate transistors gradually accumulates trapped electrons. The electric field of the trapped electrons adds to the electrons in the floating gate, lowering the window between threshold voltages for zeros vs ones. After sufficient number of rewrite cycles, the difference becomes too small to be recognizable, the cell is stuck in programmed state, and endurance failure occurs. The manufacturers usually specify the maximum number of rewrites being 1 million or more.[47]

During storage, the electrons injected into the floating gate may drift through the insulator, especially at increased temperature, and cause charge loss, reverting the cell into erased state. The manufacturers usually guarantee data retention of 10 years or more.[48]

Related types

Flash memory is a later form of EEPROM. In the industry, there is a convention to reserve the term EEPROM to byte-wise erasable memories compared to block-wise erasable flash memories. EEPROM occupies more die area than flash memory for the same capacity, because each cell usually needs a read, a write, and an erase transistor, while flash memory erase circuits are shared by large blocks of cells (often 512×8).

Newer non-volatile memory technologies such as FeRAM and MRAM are slowly replacing EEPROMs in some applications, but are expected to remain a small fraction of the EEPROM market for the foreseeable future.

Comparison with EPROM and EEPROM/flash

The difference between EPROM and EEPROM lies in the way that the memory programs and erases. EEPROM can be programmed and erased electrically using field electron emission (more commonly known in the industry as "Fowler–Nordheim tunneling").

EPROMs can't be erased electrically and are programmed by hot-carrier injection onto the floating gate. Erase is by an ultraviolet light source, although in practice many EPROMs are encapsulated in plastic that is opaque to UV light, making them "one-time programmable".

Most NOR flash memory is a hybrid style—programming is through hot-carrier injection and erase is through Fowler–Nordheim tunneling.

Type Inject electrons onto gate
(mostly interpreted as bit=0) 		Duration Remove electrons from gate
(mostly interpreted as bit=1) 		Duration/mode
EEPROM field electron emission 0.1—5 ms, bytewise field electron emission 0.1—5 ms, blockwise
NOR flash memory hot-carrier injection 0.01—1 ms field electron emission 0.01—1 ms, blockwise
EPROM hot-carrier injection 3—50 ms, bytewise UV light 5—30 minutes, whole chip

See also

References

  1. ↑ "TN-04-42: Memory Module Serial Presence-Detect". Micron Technology. 2002. https://www.micron.com/-/media/client/global/documents/products/technical-note/dram-modules/tn_04_42.pdf?rev=e5a1537ce3214de5b695f17c340fd023. 
  2. ↑ "serial presence detect (SPD)". July 2015. https://whatis.techtarget.com/definition/serial-presence-detect-SPD#:~:text=When%20a%20computer%20is%20booted,%2C%20data%20width%2C%20speed%2C%20and. 
  3. ↑ Tarui, Yasuo; Hayashi, Yutaka; Nagai, Kiyoko (1971-09-01). "Proposal of electrically reprogrammable non-volatile semiconductor memory". Proceedings of the 3rd Conference on Solid State Devices, Tokyo (The Japan Society of Applied Physics): 155–162. 
  4. ↑ Tarui, Y.; Hayashi, Y.; Nagai, K. (1972). "Electrically reprogrammable nonvolatile semiconductor memory". IEEE Journal of Solid-State Circuits 7 (5): 369–375. doi:10.1109/JSSC.1972.1052895. ISSN 0018-9200. Bibcode: 1972IJSSC...7..369T. 
  5. ↑ Tarui, Yasuo; Nagai, Kiyoko; Hayashi, Yutaka (1974-07-19). "Nonvolatile Semiconductor Memory". Oyo Buturi 43 (10): 990–1002. doi:10.11470/oubutsu1932.43.990. ISSN 2188-2290. https://www.jstage.jst.go.jp/article/oubutsu1932/43/10/43_10_990/_pdf/-char/en.pdf. 
  6. ↑ 6.0 6.1 Iizuka, H.; Masuoka, F.; Sato, Tai; Ishikawa, M. (1976). "Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure". IEEE Transactions on Electron Devices 23 (4): 379–387. doi:10.1109/T-ED.1976.18415. ISSN 0018-9383. Bibcode: 1976ITED...23..379I. 
  7. ↑ Rossler, B. (1977). "Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell". IEEE Transactions on Electron Devices 24 (5): 606–610. doi:10.1109/T-ED.1977.18788. ISSN 0018-9383. Bibcode: 1977ITED...24..606R. 
  8. ↑ Suzuki, E.; Hiraishi, H.; Ishii, K.; Hayashi, Y. (1983). "A low-voltage alterable EEPROM with metal—oxide-nitride—oxide—semiconductor (MONOS) structures". IEEE Transactions on Electron Devices 30 (2): 122–128. doi:10.1109/T-ED.1983.21085. ISSN 0018-9383. Bibcode: 1983ITED...30..122S. 
  9. ↑ XTECH, NIKKEI. "Renesas Embeds 40nm Flash Memory on Chip". http://tech.nikkeibp.co.jp/dm/english/NEWS_EN/20111215/202636/?ST=print. 
  10. ↑ "Renesas Electronics Develops 90 nm One-Transistor MONOS Flash Memory Technology to Accelerate Intelligence in Automotive Control Systems" (in en). 2016-01-03. https://www.businesswire.com/news/home/20160203006140/en/Renesas-Electronics-Develops-90-nm-One-Transistor-MONOS. 
  11. ↑ Taito, Y.; Kono, T.; Nakano, M.; Saito, T.; Ito, T.; Noguchi, K.; Hidaka, H.; Yamauchi, T. (2015). "A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170circ$ C". IEEE Journal of Solid-State Circuits 51 (1): 213–221. doi:10.1109/JSSC.2015.2467186. ISSN 0018-9200. Bibcode: 2016IJSSC..51..213.. 
  12. ↑ 12.0 12.1 Masuoka, Fujio (31 August 1972). Avalanche injection type mos memory. https://patents.google.com/patent/US3868187A/en. 
  13. ↑ Rai, Yasuki; Sasami, Terutoshi; Hasegawa, Yuzuru; Okazoe, Masaru (1973-05-18). Electrically reprogrammable nonvolatile floating gate semi-conductor memory device and method of operation. https://patents.google.com/patent/US4004159A/en. 
  14. ↑ Abbas, Shakir A.; Barile, Conrad A.; Lane, Ralph D.; Liu., Peter T (1973-03-16). "US3836992A; Electrically erasable floating gate fet memory cell". United States Patent and Trademark Office. http://pdfpiw.uspto.gov/.piw?Docid=3836992. 
  15. ↑ Frohman, Bentchkowsky D (19 October 1973). Electrically alterable floating gate device and method for altering same. https://patents.google.com/patent/US3825946A/en. 
  16. ↑ Chou, Sunlin (26 February 1973). Erasable floating gate device. https://patents.google.com/patent/US3919711A/en. 
  17. ↑ 17.0 17.1 Ohya, Shuichi; Kikuchi, Masanori (1974-12-27). Non-volatile semiconductor memory device. https://patents.google.com/patent/US4016588A/en. 
  18. ↑ Verwey, J. F.; Kramer, R. P. (1974). "Atmos—An electrically reprogrammable read-only memory device". IEEE Transactions on Electron Devices 21 (10): 631–636. doi:10.1109/T-ED.1974.17981. ISSN 0018-9383. Bibcode: 1974ITED...21..631V. 
  19. ↑ B., Roessler; R. G., Mueller (1975). "Erasable and electrically reprogrammable read-only memory using the N-channel SIMOS one-transistor cell". Siemens Forschungs und Entwicklungsberichte 4 (6): 345–351. Bibcode: 1975SiFoE...4..345R. 
  20. ↑ Jack, S; Huang, T. (8 September 1975). Semiconductor memory cell. https://patents.google.com/patent/US4051464A/en. 
  21. ↑ Gosney, W. M. (1977). "DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology". IEEE Transactions on Electron Devices 24 (5): 594–599. doi:10.1109/T-ED.1977.18786. ISSN 0018-9383. Bibcode: 1977ITED...24..594G. 
  22. ↑ Moskowitz, Sanford L. (2016) (in en). "reliability%20problems"+EPROM+1970s&pg=PA187 Advanced Materials Innovation: Managing Global Technology in the 21st century. John Wiley & Sons. ISBN 9781118986097. https://books.google.com/books?id=FyT3DAAAQBAJ&q="reliability%20problems"+EPROM+1970s&pg=PA187. 
  23. ↑ "EEPROM". https://www.tmdn.org/tmview/get-detail?st13=JP501975000139811. 
  24. ↑ "Reg. No.1342184 – LIVE – REGISTRATION – Issued and Active". https://www.j-platpat.inpit.go.jp/web/TR/JPT_1342184/1767B48BDBDDD17B2CDA0380D54389D9. 
  25. ↑ "1027459330501acc.pdf". http://archive.computerhistory.org/resources/access/text/2012/03/102745933-05-01-acc.pdf. 
  26. ↑ Harari, Eliyahou (22 February 1977). Electrically erasable non-volatile semiconductor memory. https://patents.google.com/patent/US4115914A/en. 
  27. ↑ Augusta, Benjamin (30 May 1972). Method of forming self-aligned field effect transistor and charge-coupled device. https://patents.google.com/patent/US3865652A/en. 
  28. ↑ Chen, P. C. Y. (May 1977). "Threshold-alterable Si-gate MOS devices". IEEE Transactions on Electron Devices 24 (5): 584–586. doi:10.1109/T-ED.1977.18783. ISSN 0018-9383. Bibcode: 1977ITED...24..584C. 
  29. ↑ Rossler, B. (May 1977). "Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell". IEEE Transactions on Electron Devices 24 (5): 606–610. doi:10.1109/T-ED.1977.18788. ISSN 0018-9383. Bibcode: 1977ITED...24..606R. 
  30. ↑ Simko, Richard T. (17 March 1977). "Electrically programmable and electrically erasable MOS memory cell". https://patents.google.com/patent/US4119995A/en. 
  31. ↑ Frohman-Bentchkowsky, Dov; Mar, Jerry; Perlegos, George; Johnson, William S. (15 December 1978). "Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same". https://patents.google.com/patent/US4203158A/en. 
  32. ↑ Dummer, G. W. A. (2013) (in en). Electronic Inventions and Discoveries: Electronics from Its Earliest Beginnings to the Present Day. Elsevier. ISBN 9781483145211. https://books.google.com/books?id=PbYgBQAAQBAJ&q=Intel+FLOTOX&pg=PA212. 
  33. ↑ Johnson, W.; Perlegos, G.; Renninger, A.; Kuhn, G.; Ranganath, T. (1980). "A 16Kb electrically erasable nonvolatile memory". 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. XXIII. pp. 152–153. doi:10.1109/ISSCC.1980.1156030. 
  34. ↑ Euzent, B.; Boruta, N.; Lee, J.; Jenq, C. (1981). "Reliability Aspects of a Floating Gate E2 PROM". 19th International Reliability Physics Symposium: 11–16. doi:10.1109/IRPS.1981.362965. "The Intel 2816 uses the FLOTOX structure, which has been discussed in detail in the literaturel. Basically, it uses an oxide of less than 200A thick between the floating polysilicon gate and the N+ region as shown in Figure 1.". 
  35. ↑ 2816A-2 PDF Datasheet - Intel Corporation - Datasheets360.com. Intel. October 1983. http://www.datasheets360.com/pdf/3161437977278813752. 
  36. ↑ "Seeq Technology » AntiqueTech". http://www.antiquetech.com/?page_id=900. 
  37. ↑ Rostky, George (July 2, 2002). "Remembering the PROM knights of Intel". EE Times. http://www.eetimes.com/issue/fp/showArticle.jhtml;?articleID=18307418. Retrieved 2007-02-08. 
  38. ↑ Atmel AT28C16 datasheet (0540B ed.). October 1998. http://cva.stanford.edu/classes/cs99s/datasheets/at28c16.pdf. 
  39. ↑ Gutmann, Peter (2001-08-15). "Data Remanence in Semiconductor Devices". 10th USENIX SECURITY SYMPOSIUM (IBM T. J. Watson Research Center): 39–54. http://static.usenix.org/legacy/events/sec01/full_papers/gutmann/gutmann_html/#_Ref513619292. 
  40. ↑ Janwadkar, Sudhanshu (2017-10-24). "Fabrication of Floating Gate MOS (FLOTOX)". https://www.slideshare.net/shudhanshu29/fabrication-of-floating-gate-mos-flotox. 
  41. ↑ Koga, R.; Tran, V.; George, J.; Crawford, K.; Crain, S.; Zakrzewski, M.; Yu, P.. "SEE Sensitivities of Selected Advanced Flash and First-In-First-Out Memories". The Aerospace Corporation. http://www.ti.com/pdfs/hirel/space/V3690SEE.pdf. 
  42. ↑ Fuller, Dr. Lynn (2012-02-22). CMOS Process Variations EEPROM Fabrication Technology. Microelectronic Engineering, Rochester Institute of Technology. https://people.rit.edu/lffeee/EEPROM. 
  43. ↑ Groeseneken, G.; Maes, H. E.; VanHoudt, J.; Witters, J. S.. Basics of Nonvolatile Semiconductor Memory Devices. 
  44. ↑ Bergemont, Albert; Chi, Min-Hwa (1997-05-05). "US Patent 5856222: Method of fabricating a high density EEPROM cell". National Semiconductor Corp.. https://patents.google.com/patent/US5856222A/en. 
  45. ↑ 45.0 45.1 Skorobogatov, Sergei (2017). "2017 Euromicro Conference on Digital System Design (DSD)". 2017 Euromicro Conference on Digital System Design (DSD). Vienna. pp. 244–251. doi:10.1109/DSD.2017.69. ISBN 978-1-5386-2146-2. 
  46. ↑ "Breaking copy protection in microcontrollers". https://www.cl.cam.ac.uk/~sps32/mcu_lock.html. 
  47. ↑ "Frequently Asked Questions -ROHM Semiconductor". http://www.rohm.com/products/lsi/eeprom/faq.html. 
  48. ↑ System Integration - From Transistor Design to Large Scale Integrated Circuits

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