Engineering:ARM11
| General Info | |
|---|---|
| Designed by | ARM Holdings |
| Architecture and classification | |
| Microarchitecture | ARMv6, ARMv6T2, ARMv6Z, ARMv6K |
| Instruction set | ARM (32-bit), Thumb (16-bit), Thumb-2 (32-bit) |
| History | |
ARM11 is a group of 32-bit RISC ARM processor cores licensed by ARM Holdings.[1] The ARM11 core family consists of ARM1136J(F)-S, ARM1156T2(F)-S, ARM1176JZ(F)-S, and ARM11MPCore. Since ARM11 cores were released from 2002 to 2005, they are no longer recommended for new IC designs, instead ARM Cortex-A and ARM Cortex-R cores are preferred.[1]
Overview
| Announced | |
|---|---|
| Year | Core |
| 2002 | ARM1136J(F)-S |
| 2003 | ARM1156T2(F)-S |
| 2003 | ARM1176JZ(F)-S |
| 2005 | ARM11MPCore |
The ARM11 microarchitecture (announced 29 April 2002) introduced the ARMv6 architectural additions which had been announced in October 2001. These include SIMD media instructions, multiprocessor support and a new cache architecture. The implementation included a significantly improved instruction processing pipeline, compared to previous ARM9 or ARM10 families, and is used in smartphones from Apple, Nokia, and others. The initial ARM11 core (ARM1136) was released to licensees in October 2002.
The ARM11 family are currently the only ARMv6-architecture cores. There are, however, ARMv6-M cores (Cortex-M0 and Cortex-M1), addressing microcontroller applications;[2] ARM11 cores target more demanding applications.
Differences from ARM9
In terms of instruction set, ARM11 builds on the preceding ARM9 generation. It incorporates all ARM926EJ-S features[citation needed] and adds the ARMv6 instructions for media support (SIMD) and accelerating IRQ response.
Microarchitecture improvements in ARM11 cores[3] include:
- SIMD instructions which can double MPEG-4 and audio digital signal processing algorithm speed
- Cache is physically addressed, solving many cache aliasing problems and reducing context switch overhead.
- Unaligned and mixed-endian data access is supported.
- Reduced heat production and lower overheating risk
- Redesigned pipeline, supporting faster clock speeds (target up to 1 GHz)
- Longer: 8 (vs 5) stages
- Out-of-order completion for some operations (e.g., stores)
- Dynamic branch prediction/folding (like XScale)
- Cache misses don't block execution of non-dependent instructions.
- Load/store parallelism
- ALU parallelism
- 64-bit data paths
JTAG debug support (for halting, stepping, breakpoints, and watchpoints) was simplified. The EmbeddedICE module was replaced with an interface which became part of the ARMv7 architecture. The hardware tracing modules (ETM and ETB) are compatible, but updated, versions of those used in the ARM9. In particular, trace semantics were updated to address parallel instruction execution and data transfers.
ARM makes an effort to promote recommended Verilog coding styles and techniques. This ensures semantically rigorous designs, preserving identical semantics throughout the chip design flow, which included extensive use of formal verification techniques. Without such attention, integrating an ARM11 with third-party designs could risk exposing hard-to-find latent bugs. Due to ARM cores being integrated into many different designs, using a variety of logic synthesis tools and chip manufacturing processes, the impact of its register-transfer level (RTL) quality is magnified many times.[4] The ARM11 generation focused more on synthesis than previous generations, making such concerns more of an issue.
Cores
There are four ARM11 cores:
- ARM1136[5]
- ARM1156, introduced Thumb2 instructions
- ARM1176, introduced security extensions[6]
- ARM11MPcore, introduced multicore support
Chips
- Ambarella A5s, A7, A7L
- ASPEED Technology Inc. AST25xx
- Broadcom BCM2835 (Raspberry Pi 1 A/B, Pi Zero), BCM21553
- Cavium ECONA CNS3000 series[8]
- CSR Quatro 4230, 45xx, 53xx
- Freescale Semiconductor i.MX3x series, such as i.MX31, i.MX35
- Infotmic IMAPX2xx
- Nintendo CTR-CPU (Nintendo 3DS CPU)
- NTC Module 1879VYa1Ya, K1879KhB1Ya, 1879KhK1Ya, K1888VS018
- Nvidia Tegra
- MediaTek MTK6573
- Mindspeed Comcerto 1000 (Freescale LS102MA)
- PLX Technology NAS782x
- Qualcomm MSM720x, MSM7x27
- Qualcomm Atheros AR7400
- Samsung S3C64xx, S5P64xx, S5L87xx, S5L89xx or Exynos Dual with Logic11
- Telechips TCC8902
- Texas Instruments OMAP2 series, with a TMS320 C55x or C64x DSP as a second core
- Xcometic KVM2800
See also
- ARM architecture
- List of ARM architectures and cores
- JTAG
- Interrupt, Interrupt handler
- Real-time operating system, Comparison of real-time operating systems
References
- ↑ 1.0 1.1 ARM11 Family Webpage; ARM Holdings.
- ↑ not supported by Linux as of version 3.3
- ↑ "The ARM11 Microarchitecture", ARM Ltd, 2002
- ↑ The Dangers of Living with an X (bugs hidden in your Verilog), Version 1.1 (14 October 2003).
- ↑ "ARM1136JF-S and ARM1136J-S Technical Reference Manual Revision: r1p5; ARM DDI 0211K". https://developer.arm.com/documentation/ddi0211/k/.
- ↑ "ARM1176JZF-S Technical Reference Manual Revision: r0p7". https://developer.arm.com/documentation/ddi0301/h/.
- ↑ "BCM2835 – Raspberry Pi Documentation" (in en-GB). https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2835/README.md.
- ↑ "Cavium Networks Introduces ECONA Family of Super Energy Efficient ARM®-Based System-on-Chip (SoC) Processors for the Digital Home that break the 1 Watt Barrier" (Press release). Cavium. 8 September 2009. Archived from the original on 17 November 2015. Retrieved 14 November 2015.
External links
- ARM11 official documents
- Architecture Reference Manuals: ARMv4/5/6, ARMv7-A/R
- Core Reference Manuals: ARM1136J(F)-S, ARM1156T2-S, ARM1156T2F-S, ARM1176JZ-S, ARM1176JZF-S, ARM11 MPCore
- Coprocessor Reference Manual: VFP11 (Floating-Point for ARM1136JF-S)
- Quick Reference Cards
- Instructions: Thumb (1), ARM and Thumb-2 (2), Vector Floating Point (3)
- Opcodes: Thumb (1, 2), ARM (3, 4), GNU Assembler Directives 5.
- Other
- ARM11 lacks an integer hardware division instruction
- The ARM11 Architecture, 2009, by Ian Davey and Payton Oliveri
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