Engineering:PowerPC e300
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The PowerPC e300 is a family of 32-bit PowerPC microprocessor cores developed by Freescale Semiconductor introduced in 2004. It was designed primarily for system-on-a-chip (SoC) designs with speed ranging up to 800 MHz,[1] thus making them ideal for embedded applications. It was one of the first products released by Freescale, which had formed as a spin-off of Motorola in 2004.[2]
The e300 is a superscalar RISC core with 16/16 or 32/32 kB L1 data/instruction caches, a four-stage pipeline with load/store,[3] system register, branch prediction[4] and integer unit with optional double-precision FPU.[5] The e300 core is completely backwards compatible with the G2 and PowerPC 603e cores from which it derives.[6]
The e300 core is the CPU part of several SoC processors from Freescale:
- The MPC83xx PowerQUICC II Pro family of telecom and network processors.[7]
- The MPC51xx and MPC52xx family of automotive and industrial control processors.[8]
- MSC7120 GPON, optical network processor integrated DSP unit.[9]
References
- ↑ Brown, Eric (May 13, 2009). "802.11n access point design taps new PowerQUICC chip". LinuxDevices. QuinStreet. Archived from the original on August 13, 2025. https://web.archive.org/web/20250813214711/https://linuxdevices.org/80211n-access-point-design-taps-new-powerquicc-chip/.
- ↑ Staff writer (May 3, 2004). "The Week in Review". Electronic Engineering Times (CMP Media) (1319): 8. ProQuest 208114285.
- ↑ Wright, Maury (May 23, 2012). "Designers Face Complex Choices as the Line between MCUs and Microprocessors Blurs". Electronic Products. AspenCore. https://www.digikey.com/en/articles/designers-face-complex-choices-as-the-line-between-mcus-and-microprocessors-blurs.
- ↑ Rochange, Christine; Pascal Sainrat; Sascha Uhrig (2014). Time-Predictable Architectures (ebook ed.). Wiley. ISBN 111879026X. https://www.google.com/books/edition/Time_Predictable_Architectures/SQWgAgAAQBAJ?hl=en&gbpv=1&dq=%22freescale%22+%22branch%22+%22e300%22&pg=PT84&printsec=frontcover.
- ↑ Johnson, R. Colin (August 19, 2010). "Freescale adds low-end PowerQuicc processors". EETimes (AspenCore). Archived from the original on June 9, 2026. https://web.archive.org/web/20260609043654/https://www.eetimes.com/freescale-adds-low-end-powerquicc-processors/.
- ↑ Hallinan, Christopher (2006). Embedded Linux Primer: A Practical Real-World Approach. Pearson Education. pp. 50–51. ISBN 9788131713525. https://archive.org/details/isbn_9788131713525/page/50/.
- ↑ Frenzel, Louis (September 6, 2004). "Fiber Comes Home". Electronic Design (Penton Media) 52 (19): 44. ProQuest 221039903.
- ↑ Benz, Benjamin (March 2008). "Triple-Core für Ultra-Mobile-PCs" (in de). c't (Heinz Heise): 32. https://archive.org/details/ct0825_202310/ct0803/page/32/.
- ↑ Frenzel, Louis E. (April 12, 2007). "High-Density SoC Makes GPON and FTTH Triple Play Practical and Affordable". Electronic Design (Penton Media) 55: 28. ProQuest 221008296.
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