POWER10

Short description: 2020 family of multi-core microprocessors by IBM

POWER10

General Info
Launched	2020
Designed by	IBM, OpenPower partners
Common manufacturer(s)	Samsung
Performance
Max. CPU clock rate	+3.5 GHz to +4 GHz
Cache
L1 cache	48+32 KB per core
L2 cache	2 MB per core
L3 cache	120 MB per chip
Architecture and classification
Min. feature size	7 nm
Microarchitecture	P10
Instruction set	Power ISA (Power ISA v.3.1)
Physical specifications
Cores	15 SMT8 cores 30 SMT4 cores
Package(s)	OLGA SCM and DCM
Socket(s)	1-16
History
Predecessor	POWER9

POWER10 designates a proposed superscalar, multithreading, multi-core microprocessor family, based on the open source Power ISA, and announced in August 2020 at the Hot Chips conference; systems with POWER10 CPUs are intended to reach customers in the fourth quarter of 2021.

The processor is designed to have 15 cores available, but a spare core will be included during manufacture to cost-effectively allow for yield issues.

POWER10-based processors will be manufactured by Samsung using a 7 nm process with 18 layers of metal and 18 billion transistors on a 602 mm² silicon die.

The main features of POWER10 are higher performance per watt, and better memory and I/O architectures, with a focus on artificial intelligence (AI) workloads.

Design

Each POWER10 core has doubled up on most functional units compared to its predecessor POWER9. The core is eight-way multithreaded (SMT8) and has 48 KB instruction and 32 KB data L1 caches, a 2 MB large L2 cache and a very large translation lookaside buffer (TLB) with 4096 entries. Latency cycles to the different cache stages and TLB has been reduced significantly. Each core has eight execution slices each with one floating-point unit (FPU), arithmetic logic unit (ALU), branch predictor, load–store unit and SIMD-engine, able to be fed 128-bit (64+64) instructions from the new prefix/fuse instructions of the Power ISA v.3.1. Each execution slice can handle 20 instructions each, backed up by a shared 512-entry instruction table, and fed to 128-entry-wide (64 single-threaded) load queue and 80-entry (40 single-threaded) wide store queue. Better branch prediction features have doubled the accuracy. A core has four matrix math assist (MMA) engines, for better handling of SIMD code, especially for matrix multiplication instructions where AI inference workloads have a 20-fold performance increase.

The processor has two "hemispheres" with eight cores each, sharing a 64 MB L3 cache for a total of 16 cores and 128 MB L3 caches. Due to yield issues, at least one core is always disabled, reducing L3 cache by 8 MB to a usable total of 15 cores and 120 MB L3 cache. Each chip also has eight crypto accelerators offloading common algorithms such as AES and SHA-3.

Increased clock gating and reworked microarchitecture at every stage, together with the fuse/prefix instructions enabling more work with fewer work units, and smarter cache with lower memory latencies and effective address tagging reducing cache misses, enables the POWER10 core consume half the power as POWER9. Combined with the improvements in the compute facilities by up to 30% makes the whole processor perform 2.6× better per watt than its predecessor. And in the case of mounting two cores on the same module, up to 3 times as fast in the same power budget.

As the cores can act like eight logical processors the 15-core processor looks like 120 cores to the operating system. On a dual-chip module, that becomes 240 simultaneous threads per socket.

I/O

The chips have completely reworked memory and I/O architectures. The Open Memory Interface (OMI) enables extremely low latency and high bandwidth RAM. Using serial memory communications to off chip controllers reduces signaling lanes to and from the chip, increases the bandwidth and makes the processor agnostic towards what technology is in the memory end, making the system flexible and future proofed.

The RAM can be anything from DDR3 through DDR5 to GDDR and HBM or persistent storage memory, all depending on what's practical for the application.

• DDR4 – support for up to 4 TB RAM, 410 GB/s, 10 ns latency
• GDDR6 – up to 800 GB/s
• Persistent storage – up to 2 PB

POWER10 enables encrypting of data with no performance penalty at every stage from RAM, across accelerators and cluster nodes to data at rest.

POWER10 comes with PowerAXON facility enabling chip to chip, system to system and OpenCAPI bus for accelerators, I/O and other high performance cache coherent peripherals. It manages the communications between nodes in a 16x socket SCM cluster or a 4x socket DCM cluster. It also manages the memory semantics for clustering of systems enabling load/store access from the core up to 2 PB of RAM on the entire POWER10 cluster. IBM calls this feature Memory Inception.

Both OMI and PowerAXON can handle 1 TB/s communications off the chip.

POWER10 includes PCIe 5. The SCM has 32x and the DCM has 64x PCIe 5 lanes. IBM and Nvidia agreed that including NVLink in POWER10 would be redundant since PCIe 5 is fast enough for attaching GPUs so NVLink is not present. Support for NVLink on-chip was previously a unique selling point for POWER8 and POWER9.

Variants

The POWER10 will be available in two variants, defined by firmware in the packaging. Even though the chips are identical and the difference is set in firmware, it cannot be changed by the user nor IBM themselves.

• 15× SMT8 cores
• 30× SMT4 cores

Modules

The POWER10 comes in two flip-chip plastic land grid array (FC-PLGA) packages, one single chip module (SCM) and one dual-chip module (DCM).

• SCM – 4+ GHz, up to 15 SMT8 cores. Can be clustered up to 16 sockets. x32 PCIe 5 lanes.
• DCM – 3.5+ GHz, up to 30 SMT8 cores. Can be clustered up to four sockets. x64 PCIe 5 lanes. The DCM is in the same thermal range as previous offerings.

Operating system support

• Linux, version 5.9
• PowerVM with nested Kernel-based Virtual Machine (KVM)
• AIX
• IBM i

Comparison with earlier POWER CPUs

The change to a 7-nm fabrication process results in significantly higher performance per watt.

The PowerAXON facility now extends all the way to 2 PB of unified clustered memory space, shared across multiple cluster nodes, and includes support for PCIe 5.

New SIMD instructions and new datatypes including bfloat16, INT4(INTEGER) and INT8(BIGINT). are aimed at improving AI workloads.

See also

• IBM POWER microprocessors
• OpenPOWER Foundation
• POWER9