Tiger Lake (microarchitecture)

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Short description: Intel CPU microarchitecture
Tiger Lake
Architecture and classification
Architecturex86-64
Instructionsx86-64, Intel 64
Extensions
Physical specifications
Transistors
  • 10 nm transistors
History
PredecessorIce Lake (Architecture)
SuccessorAlder Lake

Tiger Lake is an Intel CPU microarchitecture based on the third-generation 10 nm process node (named "10nm++").[1] It will replace Ice Lake,[2] representing the Optimization step in Intel's Process-Architecture-Optimization model.

Tiger Lake is slated to include quad-core 9 W TDP and 25 W TDP models.[3] It will power some 2020 "Project Athena" laptops.[4][5][6] The quad-core 96 EU die measures 13.6 by 10.7 mm (146.1 mm2), which is 19.2% wider than the 11.4 by 10.7 mm (122.5 mm2) quad-core 64 EU Ice Lake die.[7]

Features

  • Intel Willow Cove CPU cores
  • Intel Xe ("Gen12") GPU with up to 96 execution units[8] with some processors using Intel's discrete GPU, DG1[9]
  • HEVC 12-bit, 4:2:2 & 4:4:4 fixed-function hardware decoding & VP9 12-bit & 4:4:4 fixed-function hardware decoding[10]
  • PCI Express 4.0[11]
  • Thunderbolt 4[9]
  • USB4[12]
  • LPDDR5 memory [13]
  • New Deep Learning Boost (DL Boost) extensions for built-in AI training acceleration in Xeon processors[14]
  • A new AVX-512 instruction: Vector Pair Intersection to a Pair of Mask Registers (VP2INTERSECT).[15]
  • Miniaturization of CPU and motherboard into an M.2 SSD-sized small circuit board[9]

See also

References

  1. ↑ "Intel Webcast Event | 2019 Intel Investor Meeting: The Transformation of the PC Sector". May 8, 2019. http://intelstudios.edgesuite.net/im/2019/bryant.html. 
  2. ↑ Intel teases its Ice Lake & Tiger Lake family, 10nm for 2018 and 2019
  3. ↑ "2019 Intel Investor Meeting: The Transformation of the PC Sector". May 8, 2019. p. 11. http://intelstudios.edgesuite.net/im/2019/pdf/2019_Intel_Investor_Meeting_Bryant.pdf#page=11. 
  4. ↑ "Intel roadmap confirms 10nm 'Tiger Lake' chip with Xe graphics, more Ice Lake and Lakefield details" (in en). 2019-05-09. https://www.pcworld.com/article/3394342/intel-tiger-lake-chip-ice-lake-lakefield.html. 
  5. ↑ "Project Athena: An Innovation Program". https://newsroom.intel.com/press-kits/project-athena/. 
  6. ↑ "How Intel’s Project Athena is powering the future of Chromebooks". Jan 16, 2020. https://chromeunboxed.com/google-intel-project-athena-chromebooks-samsung-asus/. 
  7. ↑ Cutress, Dr Ian. "I Ran Off with Intel’s Tiger Lake Wafer. Who Wants a Die Shot?". https://www.anandtech.com/show/15380/i-ran-off-with-intels-tiger-lake-wafer-who-wants-a-die-shot. 
  8. ↑ Compute Performance of Intel® Genuine Intel® CPU 0000 with Graphics gfx-driver-user-master-28576 ReleaseInternal
  9. ↑ 9.0 9.1 9.2 Intel's Tiger Lake Laptop CPU Brings Thunderbolt 4, AI Graphics Processing
  10. ↑ https://github.com/intel/media-driver/blob/master/README.md#decodingencoding-features
  11. ↑ Intel "Tiger Lake" Supports PCIe Gen 4 and Features Xe Graphics, Phantom Canyon NUC Detailed
  12. ↑ Intel promises Thunderbolt 4 with Tiger Lake - CES 2020
  13. ↑ Intel Tiger Lake-Y 10nm CPU Makes Early Benchmark Debut With Gen12 Xe Graphics
  14. ↑ Intel makes a splash at CES with AI, autonomous driving tech and Tiger Lake chips
  15. ↑ "Compiler Support Getting Wired Up For AVX-512 VP2INTERSECT - Phoronix". https://www.phoronix.com/scan.php?page=news_item&px=LLVM-AVX512-VP2INTERSECT. 




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