Engineering:Golden Cove

Short description: CPU microarchitecture by Intel

Golden Cove

General Info
Launched	November 4, 2021 (November 4, 2021)
Designed by	Intel
Common manufacturer(s)	Intel
Performance
Max. CPU clock rate	1.0 GHz to 5.5 GHz
Cache
L1 cache	80 KB per core: 32 KB instructions 48 KB data
L2 cache	Per core: 1.25 MB (client) 2 MB (server)
Architecture and classification
Min. feature size	Intel 7 (previously known as 10ESF)
Instruction set	x86, x86-64
Extensions	AES-NI, CLMUL, RDRAND, SHA, TXT, MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, AVX2, FMA3, AVX-512, AVX-VNNI, TSX, VT-x, VT-d
Products, models, variants
Product code name(s)	Alder Lake (client) Sapphire Rapids (server, workstation)
History
Predecessor	Sunny Cove, 1S and 2S servers, 10 nm Skylake, 4S and 8S servers, 14 nm Willow Cove, mobile, 10 nm Cypress Cove, desktop, 14 nm
Successor	Raptor Cove

Golden Cove is a codename for a CPU microarchitecture developed by Intel and released in November 2021. It succeeds four microarchitectures: Sunny Cove, Skylake, Willow Cove, and Cypress Cove. It is fabricated using Intel's Intel 7 process node, previously referred to as 10 nm Enhanced SuperFin (10ESF).

The microarchitecture is used in the high-performance cores (P-core) of the 12th-generation Intel Core processors (codenamed "Alder Lake") and fourth-generation Xeon Scalable server processors (codenamed "Sapphire Rapids").

History and features

Intel first unveiled Golden Cove during their Architecture Day 2020, with further details released at the same event in August 2021. Similar to Skylake, Golden Cove was described by Intel as a major update to the core microarchitecture, with Intel stating that it would "allow performance for the next decade of compute". Intel also described Golden Cove as the largest microarchitectural upgrade to the Core family in a decade, touting a 19% increase in instructions per cycle (IPC) over Cypress Cove. At the event in 2021, Intel revealed the Gracemont and Golden Cove architectures would both be bundled in a hybrid architecture into its Alder Lake CPUs for desktops and laptops. It was described as "the successor to Intel's 10-nm Sunny Cove microarchitecture." It was also announced that the Golden Cove cores would support hyper-threading, which allows two threads to run on one core. "P-cores" based on Golden Cove stand for "performance", while "E-cores" based on Gracemont stand for "efficient."

In August 2021, Golden Cove design followed "the Willow Cove core in Tiger Lake, the Sunny Cove core in Ice Lake, and the derivative Cypress Cove core in Rocket Lake."

Succeeding Willow Cove, in 2021 the Golden Cove was described as competing against AMD's Zen 3 and Zen 4-based processors. Golden Cove is based on the 10 nm Enhanced SuperFin node by Intel, which was later renamed to Intel 7. When modifying Willow Cove, writes Hardware Times, Intel announced in 2021 that both Golden Cove and Gracemont "expanded the back and front-end, improved the out-of-order execution (OoO) capabilities, and focused more on power efficiency and real-world performance."

In January 2022, TechRadar noted that the upcoming Intel Alder Lake-P processors, mobile variants of Alder Lake with Golden Cove, could possibly use up to "six Golden Cove cores with 12 threads alongside eight Gracemont cores with eight threads," noting other permutations were also possible. In April 2022, it was reported that Raptor Lake, a "refresh" of Alder Lake, might utilize the Golden Cove and Gracemont cores. It was also reported in April 2022 that Sapphire Rapids would utilize Golden Cove cores.

Improvements

According to AnandTech in August 2021, "Intel sees the Golden Cove as a major step-function update, with massive revamps of the fundamental building blocks of the CPU, going as far as calling it as allowing performance for the next decade of compute. AnandTech in August 2021 also wrote that the last similar level of upgrades to Intel's "core front-end" was Sunny Cove, as compared to Willow Cove and Cypress Cove, which unlike Golden Cove "were more iterative designs focusing on the memory subsystem." Golden Cove was described as having "gigantic changes to the microarchitecture’s front-end", with Intel describing those changes as the largest upgrades to microarchitecture in a decade, since Skylake.

The P-core Golden Cove microarchitecture supports six-wide decode, higher than the prior four, and has split the execution ports to allow for more operations to execute at once, enabling higher IPC and ILP from workflow that can take advantage. Usually a wider decode consumes a lot more power, but Intel says that its micro-op cache (now 4K) and front-end are improved enough that the decode engine spends 80% of its time power gated."

Intel describes a number of improvements over its predecessor, Sunny Cove.

• New 6-wide partial instruction decoder (from 4-wide in previous microarchitectures) with the ability to fetch up to 32 bytes of instructions per cycle (from 16)
• Wider 6-wide microarchitecture but removed complex decoder (compared to previous 5-wide 4:1:1:1:1 design)
• μOP cache size increased to 4K entries (up from 2.25K)
• 12 execution ports (up from 10)
• Larger out-of-order instruction window compared to Sunny Cove, with the re-order buffer (ROB) size increased from 352 to 512 entries
• Larger vector/floating-point register file, which was increased from 224 to 332 entries
• 192 load and 114 store queues (from 128 and 72 in Sunny Cove)
• 1.25 MB per core L2 cache size for consumer processors and 2 MiB per core for server variants
• 3MB per core L3 cache, shared among all the cores including E-cores on Alder Lake
• Dedicated floating-point adders
• New instruction set extensions:
  • PTWRITE
  • User-mode wait (WAITPKG): TPAUSE, UMONITOR, UMWAIT
  • Architectural last branch records (LBRs)
  • Hypervisor-managed linear address translation (HLAT)
  • SERIALIZE
  • Enhanced Hardware Feedback Interface (EHFI) and HRESET
  • AVX-VNNI
  • AVX-512 with AVX512-FP16
  • In server Sapphire Rapids CPUs:
    • CLDEMOTE
    • TSX with TSXLDTRK

Products

The microarchitecture is used in the high-performance cores of the 12th generation of Intel Core hybrid processors (codenamed "Alder Lake") and the fourth generation of Xeon scalable processors (codenamed "Sapphire Rapids").

Raptor Cove

Raptor Cove

General Info
Launched	October 22, 2022 (2022-10-22)
Marketed by	Intel
Designed by	Intel
Common manufacturer(s)	Intel
Performance
Max. CPU clock rate	1.2 GHz to 6.0 GHz
Cache
L1 cache	80 KB per core: 32 KB instructions 48 KB data
L2 cache	2 MB per core
L3 cache	3 MB per core
Architecture and classification
Min. feature size	Intel 7 (previously known as 10ESF)
Instruction set	x86, x86-64
Extensions	AES-NI, CLMUL, RDRAND, SHA, TXT, MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, AVX2, FMA3, AVX-512, AVX-VNNI, TSX, VT-x, VT-d
Physical specifications
Cores	1-64
Products, models, variants
Core name(s)	Raptor Lake (client) Emerald Rapids (server)
History
Predecessor	Golden Cove
Successor	Redwood Cove

Raptor Cove, released on October 20, 2022 with Raptor Lake processors, is a refresh of the Golden Cove microarchitecture with the following changes:

• Boost frequency up to 6.0 GHz
• 2 MB L2 cache, up from 1.25 MB on the mainstream desktop variant of Golden Cove. The server variant of the previous Golden Cove core already had 2 MB L2 cache per core.
• New dynamic prefetch algorithm

They are also used in the Emerald Rapids server processors.

Since Raptor Cove is basically identical to Golden Cove, 13th Gen Core models come with B0 stepping use Raptor Cove exclusively while others with different steppings (such as C0, H0, J0 and Q0) still use Golden Cove. Notably, some models come with multiple steppings (such as i5-13400F and i7-13700HX) are using a different microarchitecture but they are selling at the same time.

See also

• List of Intel CPU microarchitectures