Engineering:MCDRAM

Short description: 3D-stacked DRAM

Multi-Channel DRAM or MCDRAM (pronounced em cee dee ram) is a 3D-stacked DRAM that is used in the Intel Xeon Phi processor codenamed Knights Landing. It is a version of Hybrid Memory Cube developed in partnership with Micron Technology, and a competitor to High Bandwidth Memory.

The many cores in the Xeon Phi processors, along with their associated vector processing units, enable them to consume many more gigabytes per second than traditional DRAM DIMMs can supply. The "Multi-channel" part of the MCDRAM full name reflects the cores having many more channels available to access the MCDRAM than processors have to access their attached DIMMs. This high channel count leads to MCDRAM's high bandwidth, up to 400+ GB/s, although the latencies are similar to a DIMM access.

Its physical placement on the processor imposes some limits on capacity – up to 16 GB at launch, although speculated to go higher in the future.

Programming

The memory can be partitioned at boot time, with some used as cache for more distant DDR, and the remainder mapped into the physical address space.

The application can request pages of virtual memory to be assigned to either the distant DDR directly, to the portion of DDR that is cached by the MCDRAM, or to the portion of the MCDRAM that is not being used as cache. One way to do this is via thememkind API.

When used as cache, the latency of a miss accessing both the MCDRAM and DDR is slightly higher than going directly to DDR, and so applications may need to be tuned to avoid excessive cache misses.

External links

• MCDRAM (High Bandwidth Memory) on Knights Landing – Analysis Methods & Tools
• An Intro to MCDRAM (High Bandwidth Memory) on Knights Landing
• High Bandwidth Memory (HBM): how will it benefit your application?
• Micron HMC Webinar July 2017 slides