Template:Processor technologies

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Processor technologies

Instruction set
architectures

Types	CISC RISC Application-specific EDGE TRIPS VLIW EPIC MISC OISC NISC ZISC comparison addressing modes

Instruction pipelining	Pipeline stall Operand forwarding Classic RISC pipeline
Hazards	Data dependency Structural Control False sharing
Out-of-order	Tomasulo algorithm Reservation station Re-order buffer Register renaming
Speculative	Branch prediction Memory dependence prediction

Level	Bit Bit-serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory Distributed
Multithreading	Temporal Simultaneous Hyperthreading Speculative Preemptive Cooperative
Flynn's taxonomy	SISD SIMD SWAR SIMT MISD MIMD SPMD

Processor
performance

Transistor count
Instructions per cycle (IPC)
- Cycles per instruction (CPI)
Instructions per second (IPS)
Floating-point operations per second (FLOPS)
Transactions per second (TPS)
Synaptic updates per second (SUPS)
Performance per watt (PPW)
Cache performance metrics
Computer performance by orders of magnitude

By application	Microprocessor Microcontroller Mobile Notebook Ultra-low-voltage ASIP
Systems on chip	System on a chip (SoC) Multiprocessor (MPSoC) Programmable (PSoC) Network on a chip (NoC)
Hardware accelerators	AI accelerator Vision processing unit (VPU) Physics processing unit (PPU) Digital signal processor (DSP) Tensor processing unit (TPU) Secure cryptoprocessor Network processor Baseband processor

Core count

Components

Functional units	Arithmetic logic unit (ALU) Address generation unit (AGU) Floating-point unit (FPU) Memory management unit (MMU) Load–store unit Translation lookaside buffer (TLB) Integrated memory controller (IMC)
Logic	Combinational Sequential Glue Logic gate Quantum Array
Registers	Processor register Status register Stack register Register file Memory buffer Program counter
Control unit	Instruction unit Data buffer Write buffer Microcode ROM Counter
Datapath	Multiplexer Demultiplexer Adder Multiplier CPU Binary decoder Address decoder Sum addressed decoder Barrel shifter
Circuitry	Integrated circuit 3D Mixed-signal Power management Boolean Digital Analog Quantum Switch

Power
management

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