Manycore processor

From HandWiki
Jump to: navigation, search

Manycore processors are specialist multi-core processors designed for a high degree of parallel processing, containing numerous simpler, independent processor cores (from a few tens of cores to thousands or more). Manycore processors are used extensively in embedded computers and high-performance computing.

Contrast with multicore architecture

Manycore processors are distinct from multi-core processors in being optimized from the outset for a higher degree of explicit parallelism, and for higher throughput (or lower power consumption) at the expense of latency and lower single thread performance.

The broader category of multi-core processors, by contrast, are usually designed to efficiently run both parallel and serial code, and therefore place more emphasis on high single thread performance (e.g. devoting more silicon to out of order execution, deeper pipelines, more superscalar execution units, and larger, more general caches), and shared memory. These techniques devote runtime resources toward figuring out implicit parallelism in a single thread. They are used in systems where they have evolved continuously (with backward compatibility) from single core processors. They usually have a 'few' cores (e.g. 2,4,8), and may be complemented by a manycore accelerator (such as a GPU) in a heterogeneous system.

Motivation

Cache coherency is an issue limiting the scaling of multicore processors. Manycore processors may bypass this with methods such as message passing,[1] scratchpad memory, DMA,[2] partitioned global address space,[3] or read-only/non-coherent caches. A manycore processor using a network on a chip and local memories gives software the opportunity to explicitly optimise the spatial layout of tasks (e.g. as seen in tooling developed for TrueNorth).[4]

Manycore processors may have more in common (conceptually) with technologies originating in high performance computing such as clusters and vector processors.[5]

GPUs may be considered a form of manycore processor having multiple shader processing units, and only being suitable for highly parallel code (high throughput, but extremely poor single thread performance).

Suitable programming models

Classes of manycore systems

Specific manycore architectures

  • ZettaScaler [1], Japanese PEZY Computing 2048-core modules
  • Xeon Phi coprocessor,[8] which has MIC (Many Integrated Cores) architecture
  • Tilera
  • Adapteva Epiphany Architecture, a manycore chip using PGAS scratchpad memory
  • Coherent Logix hx3100 Processor, a 100-core DSP/GPP processor based on HyperX Architecture
  • Movidius Myriad 2, a manycore Vision processing unit
  • Kalray, a manycore PCI-e accelerator for data-intensive tasks
  • Teraflops Research Chip a manycore processor using message passing
  • TrueNorth an AI accelerator with a manycore network on a chip architecture
  • Green arrays a manycore processor using message passing aimed at low power applications
  • Eyeriss, a manycore processor designed for running convolutional neural nets for embedded vision applications[9]

Specific manycore computers with 1M+ CPU cores

A number of computers built from multicore processors have one million or more individual CPU cores. Examples include:

See also

References

  1. Mattson, Tim (January 2010). "The Future of Many Core Computing: A tale of two processors". https://cseweb.ucsd.edu/classes/fa12/cse291-c/talks/SCC-80-core-cern.pdf. 
  2. Hendry, Gilbert; Kretschmann, Mark. "IBM Cell Processor". http://meseec.ce.rit.edu/756-projects/spring2006/d2/6/cell-architecture-final.pdf. 
  3. Olofsson, Andreas; Nordström, Tomas; Ul-Abdin, Zain (2014). "Kickstarting High-performance Energy-efficient Manycore Architectures with Epiphany". arXiv:1412.5538 [cs.AR].
  4. Amir, Arnon (June 11, 2015). "IBM SyNAPSE Deep Dive Part 3". IBM Research. https://www.youtube.com/watch?v=6O6igM4lMDc. 
  5. "cell architecture". http://www.blachford.info/computer/Cell/Cell1_v2.html. "The Cell architecture is like nothing we have ever seen in commodity microprocessors, it is closer in design to multiprocessor vector supercomputers"
  6. Rick Merritt (June 20, 2011), "OEMs show systems with Intel MIC chips", www.eetimes.com (EE Times), http://www.eetimes.com/electronics-news/4217092/OEMs-show-systems-with-Intel-MIC-chips 
  7. Barker, J; Bowden, J (2013). "Manycore Parallelism through OpenMP". IWOMP. Springer. doi:10.1007/978-3-642-40698-0_4. 
  8. Mittal, Sparsh; Anand, Osho; Kumarr, Visnu P (May 2019). "A Survey on Evaluating and Optimizing Performance of Intel Xeon Phi". https://www.researchgate.net/publication/333384596_A_Survey_on_Evaluating_and_Optimizing_Performance_of_Intel_Xeon_Phi. 
  9. "Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks". IEEE International Solid-State Circuits Conference, ISSCC 2016, Digest of Technical Papers. 2016. pp. 262–263. https://www.mit.edu/~sze/eyeriss.html. 

External links







Hostmonster hHosting Tier.Net hosting HandWiki ads