Operand forwarding

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Operand forwarding (or data forwarding) is an optimization in pipelined CPUs to limit performance deficits which occur due to pipeline stalls.[1][2] A data hazard can lead to a pipeline stall when the current operation has to wait for the results of an earlier operation which has not yet finished.

Example

ADD A B C  #A=B+C
SUB D C A  #D=C-A

If these two assembly pseudocode instructions run in a pipeline, after fetching and decoding the second instruction, the pipeline stalls, waiting until the result of the addition is written and read.

Without operand forwarding
1 2 3 4 5 6 7 8
Fetch ADD Decode ADD Read Operands ADD Execute ADD Write result
Fetch SUB Decode SUB stall stall Read Operands SUB Execute SUB Write result
With operand forwarding
1 2 3 4 5 6 7
Fetch ADD Decode ADD Read Operands ADD Execute ADD Write result
Fetch SUB Decode SUB stall Read Operands SUB: use result from previous operation Execute SUB Write result

Technical realization

The CPU control unit must implement logic to detect dependencies where operand forwarding makes sense. A multiplexer can then be used to select the proper register or flip-flop to read the operand from.

See also

References

  1. "CMSC 411 Lecture 19, Pipelining Data Forwarding". University of Maryland Baltimore County Computer Science and Electrical Engineering Department. http://www.csee.umbc.edu/~squire/cs411_l19.html. Retrieved 2020-01-22. 
  2. "High performance computing, Notes of class 11". hpc.serc.iisc.ernet.in. September 2000. Archived from the original on 2013-12-27. https://web.archive.org/web/20131227033204/http://hpc.serc.iisc.ernet.in/~govind/hpc/L10-Pipeline.txt. Retrieved 2014-02-08. 

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