Zero instruction set computer

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In computer science, zero instruction set computer (ZISC) refers to a computer architecture based solely on pattern matching and absence of (micro-)instructions in the classical[clarification needed] sense. These chips are known for being thought of as comparable to the neural networks, being marketed for the number of "synapses" and "neurons".[1]

The acronym ZISC alludes to reduced instruction set computer (RISC).[citation needed]


ZISC is a hardware implementation of Kohonen networks (artificial neural networks) allowing massively parallel processing of very simple data (0 or 1). This hardware implementation was invented by Guy Paillet, developed in cooperation with the IBM chip factory of Essonnes, in France, and was commercialized by IBM.


The ZISC architecture alleviates the memory bottleneck by blending pattern memory with pattern learning and recognition logic.

Their massively parallel computing solves the by allotting each "neuron" its own memory and allowing simultaneous problem-solving the results of which are settled up disputing with each other.[2]

Applications and controversy

According to TechCrunch, software emulations of these types of chips are currently used for image recognition by many large tech companies, such as Facebook and Google. When applied to other miscellaneous pattern detection tasks, such as with text, results are said to be produced in microseconds even with chips released in 2007.[1]

Junko Yoshida, of the EE Times, compared the NeuroMem chip with "The Machine", a machine capable of being able to predict crimes from scanning people's faces, from Person of Interest (TV series) describing it as "the heart of big data" and "foreshadow[ing] a real-life escalation in the era of massive data collection".[3]

See also


External links

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